Freescale Semiconductor PowerPC e500 Core - Page 15

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor xv
Contents
Paragraph
Number Title
Page
Number
8.4.6 Interrupt Taken Debug Event..................................................................................... 8-13
8.4.7 Return Debug Event................................................................................................... 8-13
8.4.8 Unconditional Debug Event....................................................................................... 8-14
Part II
e500 Core Complex
Chapter 9
Timer Facilities
9.1 Timer Facilities ................................................................................................................ 9-1
9.2 Timer Registers................................................................................................................9-2
9.3 The e500 Timer Implementation...................................................................................... 9-3
9.3.1 Alternate Time Base APU ........................................................................................... 9-4
9.3.2 Performance Monitor Time Base Event ...................................................................... 9-4
Chapter 10
Auxiliary Processing Units (APUs)
10.1 Overview........................................................................................................................ 10-1
10.2 Branch Target Buffer (BTB) Locking APU................................................................... 10-2
10.2.1 BTB Locking APU Programming Model.................................................................. 10-2
10.2.1.1 BTB Locking APU Instructions ............................................................................ 10-2
10.2.1.2 BTB Locking APU Registers ................................................................................ 10-3
10.3 Alternate Time Base APU.............................................................................................. 10-3
10.3.1 Programming Model.................................................................................................. 10-3
10.4 Double-Precision Floating-Point APU (e500 v2 Only)................................................. 10-4
10.4.1 Programming Model.................................................................................................. 10-4
10.4.2 Double-Precision Floating-Point APU Operations.................................................... 10-4
10.4.2.1 Operational Modes................................................................................................. 10-4
10.4.2.2 Floating-Point Data Formats.................................................................................. 10-5
10.4.2.3 Overflow and Underflow....................................................................................... 10-6
10.4.3 Instruction Descriptions............................................................................................. 10-6
10.4.4 Embedded Floating-Point Results Summary........................................................... 10-22
10.4.5 Floating-Point Conversion Models.......................................................................... 10-22
10.4.5.1 Common Functions.............................................................................................. 10-22
10.4.5.2 Convert from Double-Precision Floating-Point to Integer Word
with Saturation................................................................................................. 10-23
10.4.5.3 Convert to Double-Precision Floating-Point from Integer Word
with Saturation................................................................................................. 10-25