Freescale Semiconductor PowerPC e500 Core - Page 16

PowerPC e500 Core Family Reference Manual, Rev. 1
xvi Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
Chapter 11
L1 Caches
11.1 Overview........................................................................................................................ 11-1
11.1.1 Block Diagram........................................................................................................... 11-3
11.1.1.1 Load/Store Unit (LSU) .......................................................................................... 11-3
11.1.1.1.1 Caching-Allowed Loads and the LSU............................................................... 11-4
11.1.1.1.2 Store Queue ....................................................................................................... 11-4
11.1.1.1.3 L1 Load Miss Queue (LMQ)............................................................................. 11-4
11.1.1.1.4 Data Line Fill Buffer (DLFB)............................................................................ 11-4
11.1.1.1.5 Data Write Buffer (DWB) ................................................................................. 11-5
11.1.1.2 Instruction Unit...................................................................................................... 11-5
11.1.1.3 Core Interface Unit ................................................................................................ 11-5
11.2 L1 Cache Organization .................................................................................................. 11-6
11.2.1 L1 Data Cache Organization...................................................................................... 11-6
11.2.2 L1 Instruction Cache Organization............................................................................ 11-7
11.2.3 L1 Cache Parity ......................................................................................................... 11-8
11.2.4 Cache Parity Error Injection ...................................................................................... 11-9
11.3 Cache Coherency Support ............................................................................................. 11-9
11.3.1 Data Cache Coherency Model................................................................................... 11-9
11.3.2 Instruction Cache Coherency Model ........................................................................11-11
11.3.3 Snoop Signaling....................................................................................................... 11-12
11.3.4 WIMGE Settings and Effect on L1 Caches............................................................. 11-13
11.3.4.1 Write-Back Stores................................................................................................ 11-13
11.3.4.2 Write-Through Stores .......................................................................................... 11-13
11.3.4.3 Caching-Inhibited Loads and Stores.................................................................... 11-13
11.3.4.4 Misaligned Accesses and the Endian (E) Bit....................................................... 11-13
11.3.4.5 Speculative Accesses to Guarded Memory ......................................................... 11-13
11.3.5 Load/Store Operations ............................................................................................. 11-14
11.3.5.1 Performed Loads and Stores................................................................................ 11-14
11.3.5.2 Sequential Consistency of Memory Accesses..................................................... 11-15
11.3.5.3 Enforcing Store Ordering with Respect to Loads................................................ 11-15
11.3.5.4 Atomic Memory References................................................................................ 11-15
11.4 L1 Cache Control......................................................................................................... 11-16
11.4.1 Cache Control Instructions ...................................................................................... 11-16
11.4.2 L1 Instruction and Data Cache Enabling/Disabling................................................ 11-18
11.4.3 L1 Instruction and Data Cache Flash Invalidation .................................................. 11-18
11.4.4 L1 Instruction and Data Cache Line Locking/Unlocking........................................ 11-19
11.4.4.1 Effects of Other Cache Instructions on Locked Lines......................................... 11-21
11.4.4.2 Flash Clearing of Lock Bits................................................................................. 11-21