Freescale Semiconductor PowerPC e500 Core - Page 17

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor xvii
Contents
Paragraph
Number Title
Page
Number
11.5 L1 Data Cache Flushing .............................................................................................. 11-22
11.6 L1 Cache Operation..................................................................................................... 11-22
11.6.1 Cache Miss and Reload Operations......................................................................... 11-23
11.6.1.1 Data Cache Fills................................................................................................... 11-23
11.6.1.2 Instruction Cache Fills......................................................................................... 11-23
11.6.1.3 Cache Allocation on Misses ................................................................................ 11-24
11.6.1.4 Store Miss Merging ............................................................................................. 11-24
11.6.1.5 Store Hit to a Data Cache Block Marked Shared ................................................ 11-24
11.6.1.6 Data Cache Block Push Operation ...................................................................... 11-24
11.6.2 L1 Cache Block Replacement.................................................................................. 11-25
11.6.2.1 PLRU Replacement ............................................................................................. 11-25
11.6.2.2 PLRU Bit Updates............................................................................................... 11-26
11.6.2.3 Cache Locking and PLRU................................................................................... 11-27
11.7 L2 Cache Support ........................................................................................................ 11-27
11.7.1 Invalidating the L2 Cache after a Cache Tag Parity Error....................................... 11-27
11.7.2 L2 Locking............................................................................................................... 11-27
11.7.2.1 L2 Unlocking....................................................................................................... 11-28
11.7.2.2 L1 Overlock......................................................................................................... 11-28
Chapter 12
Memory Management Units
12.1 e500 MMU Overview.................................................................................................... 12-1
12.1.1 MMU Features........................................................................................................... 12-1
12.1.2 TLB Entry Maintenance Features.............................................................................. 12-3
12.2 Effective-to-Real Address Translation........................................................................... 12-4
12.2.1 Virtual Addresses with Three PID Registers ............................................................. 12-5
12.2.2 Variable-Sized Pages.................................................................................................. 12-6
12.2.3 Checking for TLB Entry Hit...................................................................................... 12-7
12.2.4 Checking for Access Permissions.............................................................................. 12-7
12.3 Translation Lookaside Buffers (TLBs).......................................................................... 12-8
12.3.1 L1 TLB Arrays........................................................................................................... 12-9
12.3.2 L2 TLB Arrays......................................................................................................... 12-11
12.3.2.1 IPROT Invalidation Protection in TLB1 ............................................................. 12-12
12.3.2.2 Replacement Algorithms for L2 MMU ............................................................... 12-13
12.3.2.2.1 Round-Robin Replacement for TLB0—e500v1.............................................. 12-14
12.3.2.2.2 Round-Robin Replacement for TLB0—e500v2.............................................. 12-14
12.3.3 Consistency Between L1 and L2 TLBs................................................................... 12-15
12.3.4 L1 and L2 TLB Access Times................................................................................. 12-16
12.3.5 The G Bit (of WIMGE) ........................................................................................... 12-16