Freescale Semiconductor PowerPC e500 Core - Page 18

PowerPC e500 Core Family Reference Manual, Rev. 1
xviii Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
12.3.6 TLB Entry Field Definitions.................................................................................... 12-17
12.4 TLB Instructions—Implementation............................................................................. 12-17
12.4.1 TLB Read Entry (tlbre) Instruction......................................................................... 12-18
12.4.1.1 Reading Entries from the TLB1 Array................................................................ 12-18
12.4.1.2 Reading Entries from the TLB0 Array................................................................ 12-18
12.4.2 TLB Write Entry (tlbwe) Instruction....................................................................... 12-19
12.4.2.1 Writing to the TLB1 Array .................................................................................. 12-19
12.4.2.2 Writing to the TLB0 Array .................................................................................. 12-19
12.4.3 TLB Search (tlbsx) Instruction—Searching the TLB1 and TLB0 Arrays.............. 12-19
12.4.4 TLB Invalidate (tlbivax) Instruction....................................................................... 12-20
12.4.4.1 TLB Selection for tlbivax Instruction ................................................................. 12-21
12.4.4.2 Invalidate All Address Encoding for tlbivax Instruction.................................... 12-22
12.4.4.3 TLB Invalidate Broadcast Enabling .................................................................... 12-22
12.4.5 TLB Synchronize (tlbsync) Instruction................................................................... 12-22
12.5 TLB Entry Maintenance—Details ............................................................................... 12-22
12.5.1 Automatic Updates—TLB Miss Exceptions ........................................................... 12-23
12.5.2 TLB Interrupt Routines............................................................................................ 12-24
12.5.2.1 Permissions Violations (ISI, DSI) Interrupt Handlers........................................ 12-24
12.6 TLB States after Reset ................................................................................................. 12-24
12.7 Core Complex MMU Registers ................................................................................... 12-25
12.7.1 e500 MAS Registers................................................................................................ 12-26
12.7.1.1 MAS Register 7 (MAS7)..................................................................................... 12-31
12.7.2 MAS Register Updates ............................................................................................ 12-32
Chapter 13
Core Complex Bus (CCB)
13.1 Overview........................................................................................................................ 13-1
13.2 Signal Summary............................................................................................................. 13-2
13.3 Core Interface Behavior................................................................................................. 13-5
13.3.1 Parity Specification.................................................................................................... 13-5
13.3.2 msync Operation and the Bus.................................................................................... 13-6
13.3.3 mbar Operation and the Bus..................................................................................... 13-6
13.4 Address Streaming Mode............................................................................................... 13-7
13.5 L2 Cache Support .......................................................................................................... 13-7
13.5.1 L2 Locking................................................................................................................. 13-7
13.5.2 L2 Unlocking............................................................................................................. 13-8
13.5.3 L1 Overlock............................................................................................................... 13-8
13.6 Reservation Management .............................................................................................. 13-8
13.7 Remote Atomic Status Monitoring................................................................................ 13-9
13.8 Proper Reporting of Bus Faults ..................................................................................... 13-9