Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 3-35
• Another processor executes a dcba to the reservation granule. The reservation is lost if the
instruction causes the target block to be newly established in the data cache or to be
modified; otherwise, whether the reservation is lost is undefined.
• Some other mechanism modifies a location in the same reservation granule.
Interrupts are not guaranteed to clear reservations. (However, system software invoked by
interrupts may clear reservations.)
In general, programming conventions must ensure that lwarx and stwcx. specify addresses that
match; a stwcx. should be paired with a specific lwarx to the same location. Situations in which a
stwcx. may erroneously be issued after some lwarx other than that with which it is intended to be
paired must be scrupulously avoided. For example, there must not be a context switch in which
the processor holds a reservation on behalf of the old context, and the new context resumes after
a lwarx and before the paired stwcx.. The stwcx. in the new context might succeed, which is not
what was intended by the programmer.
Such a situation must be prevented by issuing a stwcx. to a dummy writable word-aligned location
as part of the context switch, thereby clearing any reservation established by the old context.
Executing stwcx. to a word-aligned location is enough to clear the reservation.
In the e500, a reservation is lost for any of the following reasons:
• Execution of a stwcx.
• Any of the following interrupts occur:
— External
— Performance monitor
— Critical input interrupt
— Machine check
— Fixed-interval timer
— Decrementer
— Unconditional debug event
— Watchdog timer
• Snoops
— RWITM, RCLAIM
— Writes, flush, kill, dkill
• Another processor executes any of the following to the reservation granule:
— dcbtst
— dcbf
—dcba
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