Freescale Semiconductor PowerPC e500 Core - Page 360

PowerPC e500 Core Family Reference Manual, Rev. 1
10-24 Freescale Semiconductor
Auxiliary Processing Units (APUs)
CnvtFP64ToI32Sat(fp, signed, round, fractional)
FP64format fp;
if (Isa64NaNorInfinity(fp)) then // SNaN, QNaN, +-INF
SignalFPError(LOWER, FINV)
if (Isa64NaN(fp)) then
return 0x00000000 // all NaNs
if (signed = SIGN) then
if (fp
sign
= 1) then
return 0x80000000
else
return 0x7fffffff
else
if (fp
sign
= 1) then
return 0x00000000
else
return 0xffffffff
if (Isa64Denorm(fp)) then
SignalFPError(LOWER, FINV)
return 0x00000000 // regardless of sign
if ((signed = UNSIGN) & (fp
sign
= 1)) then
SignalFPError(LOWER, FOVF) // overflow
return 0x00000000
if ((fp
exp
= 0) & (fp
frac
= 0)) then
return 0x00000000 // all zero values
if (fractional = I) then // convert to integer
max_exp ← 1054
shift ← 1054 - fp
exp
if (signed ← SIGN) then
if ((fp
exp
≠ 1054) | (fp
frac
≠ 0) | (fp
sign
≠ 1)) then
max_exp ← max_exp - 1
else // fractional conversion
max_exp ← 1022
shift ← 1022 - fp
exp
if (signed = SIGN) then
shift ← shift + 1
if (fp
exp
> max_exp) then
SignalFPError(LOWER, FOVF) // overflow
if (signed = SIGN) then
if (fp
sign
= 1) then
return 0x80000000
else
return 0x7fffffff
else
return 0xffffffff
result ← 0b1 || fp
frac[0:30]
// add U to frac
guard ← fp
frac[31]
sticky ← (fp
frac[32:63]
≠ 0)
for (n ← 0; n < shift; n ← n + 1) do
sticky ← sticky | guard
guard ← result & 0x00000001
result ← result > 1
// Report sticky and guard bits
SPEFSCR
FG
← guard
SPEFSCR
FX
← sticky
if (guard | sticky) then
SPEFSCR
FINXS
← 1
// Round the result
if ((round = ROUND) & (SPEFSCR
FINXE
= 0)) then
if (SPEFSCR
FRMC
= 0b00) then // nearest