Freescale Semiconductor PowerPC e500 Core - Page 379

L1 Caches
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 11-17
If a cache instruction causes multiple no-op or exception conditions, the results are determined by
the order of precedence described in Table 11-7. The priority of the conditions decreases from left
to right and the dashes indicate that the operation executes normally. Note that a dash in this table
indicates that a failure does not occur under the conditions described.
Note that CE corresponds to the cache enable bit in L1CSR1 (for the instruction cache) or L1CSR0
(for the data cache). DLK and ILK indicate that the condition causes a data storage interrupt and
sets the ESR[DLK] or ESR[ILK]. CUL indicates the unable-to-lock condition that results in a
no-op and sets L1CSR1[ICUL] or L1CSR0[CUL].
Acronyms are used to signify the following interrupts:
• DTLB (data TLB interrupt)
• ALI (alignment interrupt)
• DSI (data storage interrupt)
icbt Instruction Cache Touch no-op x
icbtls Instruction Cache Block Touch and Lock Set x
Table 11-7. Failed Cache Events
Operation MMU Miss
MSR[PR] = 1
MSR[UCLE] = 0
Protection Violation CT = CE = 0 CT ≠ 0 or 1 CI WT
dcbt
dcbtst
no-op
no-op
—
1
—
1
These instructions are not affected by the value of UCLE
no-op
no-op
—
—
no-op
no-op
no-op
no-op
—
no-op
dcbtls
dcbtstls
dcblc
DTLB
DTLB
DTLB
DLK
DLK
DLK
DSI
DSI
DSI
CUL
CUL
no-op
CUL
CUL
no-op
CUL
CUL
—
—
CUL
—
icbtls
icblc
DTLB
DTLB
ILK
ILK
DSI
DSI
CUL
no-op
CUL
no-op
CUL
—
—
—
dcbz
2
dcba
2
2
These instructions do not use a CT operand.
DTLB
no-op
—
—
DSI
no-op
—— —
—
ALI
no-op
ALI
no-op
dcbf
2
dcbi
2
icbi
2
DTLB
DTLB
DTLB
—
—
—
DSI
DSI
DSI
—
—
—
—
—
—
—
—
—
—
—
—
lwarx
2
stwcx.
2
DTLB
DTLB
—
—
DSI
DSI
—
—
—
—
—
—
DSI
DSI
Load
2
Store
2
DTLB
DTLB
—
—
DSI
DSI
—
—
—
—
—
—
—
—
Table 11-6. Cache Instruction Comparison (continued)
Mnemonic Instruction e500 Core Book E AIM Architecture