PowerPC e500 Core Family Reference Manual, Rev. 1
12-2 Freescale Semiconductor
Memory Management Units
The level 1 MMUs have the following features:
• Two 4-entry, fully-associative TLB arrays (one for instruction accesses and one for data
accesses) supporting the nine (e500v1) or eleven (e500v2) page sizes shown in Table 12-2
• Two 64-entry, 4-way set-associative TLB arrays (one for instruction accesses and one for
data accesses) that support only 4-Kbyte pages
• L1 MMU access occurs in parallel with L1 cache access time (address translation/L1 cache
access can be fully pipelined so one load/store can be completed on every clock).
• Performs an L1 TLB lookup for an instruction access in parallel with an L1 TLB lookup
for a data access
• All L1 TLB entries are a proper subset of TLB entries resident in L2 MMU (completely
maintained by the hardware).
• Automatically performs invalidations to maintain consistency with L2 TLBs
The level 2 MMU has the following features:
• A 16-entry, fully-associative unified (for instruction and data accesses) L2 TLB array
(TLB1) supports the nine (e500v1) or eleven (e500v2) page sizes shown in Table 12-2.
• A 256-entry, 2-way (e500v1) or 512-entry, 4-way (e500v2) set-associative unified (for
instruction and data accesses) L2 TLB array (TLB0) supports only 4-Kbyte pages.
• Hardware assistance for TLB miss exceptions
• TLB1 and TLB0 managed by tlbre, tlbwe, tlbsx, tlbsync, tlbivax, and mtspr instructions
• Performs invalidations in TLB1 and TLB0 caused by tlbivax instructions executed by this
core. Also supports snooping of TLB1 and TLB0 for invalidation caused by tlbivax
instructions executed by other masters.
• IPROT bit implemented in TLB1 prevents invalidations, protecting critical entries (so
designated by having the IPROT bit set) from being invalidated.
To Next Page
Loading...
