PowerPC e500 Core Family Reference Manual, Rev. 1
1-4 Freescale Semiconductor
Core Complex Overview
The processor core integrates two simple instruction units (SU1, SU2), a multiple-cycle
instruction unit (MU), a branch unit (BU), and a load/store unit (LSU).
The LSU and SU2 support 64- and 32-bit instructions.
The ability to execute five instructions in parallel and the use of simple instructions with short
execution times yield high efficiency and throughput. Most integer instructions execute in 1 clock
cycle. A series of independent vector floating-point add instructions can be issued and completed
with a throughput of one instruction per cycle.
The core complex includes independent on-chip, 32-Kbyte, eight-way set-associative, physically
addressed caches for instructions and data. It also includes on-chip first-level instruction and data
memory management units (MMUs) and an on-chip second-level unified MMU.
• The first-level MMUs contain two four-entry, fully-associative instruction and data
translation lookaside buffer (TLB) arrays that provide support for demand-paged virtual
memory address translation and variable-sized pages. They also contain two 64-entry,
4-way set-associative instruction and data TLB arrays that support 4-Kbyte pages. These
arrays are maintained entirely by the hardware with a true least-recently-used (LRU)
algorithm.
• The second-level MMU contains a 16-entry, fully-associative unified (instruction and data)
TLB array that provides support for variable-sized pages. It also contains a unified TLB for
4-Kbyte page size support, as follows:
— a 256-entry, 2-way set-associative unified TLB for the e500v1
— a 512-entry, 4-way set-associative unified TLB for the e500v2
These second-level TLBs are maintained completely by the software.
The core complex allows cache-line-based user-mode locks on the contents in either the instruction
or data cache. This provides embedded applications with the capability for locking interrupt
routines or other important (time-sensitive) instruction sequences into the instruction cache. It also
allows data to be locked into the data cache, which supports deterministic execution time.
The core complex supports a high-speed on-chip internal bus with data tagging called the core
complex bus (CCB). The CCB has two general-purpose read data buses, one write data bus, data
parity bits, data tag bits, an address bus, and address attribute bits. The processor core complex
supports out-of-order reads, in-order writes, and one level of pipelining for addresses with
address-retry responses. It can also support single-beat and burst data transfers for memory
accesses and memory-mapped I/O operations.
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