Core Complex Overview
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 1-7
– 64-bit loads and stores
– 64-bit merge instructions
• Cache structure—Separate 32-Kbyte, 32-byte line, 8-way set-associative level 1 instruction
and data caches
— 1.5-cycle cache array access, 3-cycle load-to-use latency
— Pseudo-LRU (PLRU) replacement algorithm
— Copy-back data cache that can function as a write-through cache on a page-by-page basis
— Supports all Book E memory coherency modes
— Supports EIS-defined cache-locking instructions, as listed in Table 1-3
• Dual-issue superscalar control
— Two-instructions-per-clock peak issue rate
— Precise exception handling
• Decode unit
— 12-entry instruction queue (IQ)
— Full hardware detection of interlocks
— Decodes as many as two instructions per cycle
— Decode serialization control
— Register dependency resolution and renaming
• Branch prediction unit (BPU)
— Dynamic branch prediction using a 512-entry, 4-way set-associative branch target
buffer (BTB) supported by the e500 BTB instructions listed in Table 1-5.
— Branch prediction is handled in the fetch stages.
• Completion unit
— As many as 14 instructions allowed in 14-entry completion queue (CQ)
— In-order retirement of as many as two instructions per cycle
— Completion and refetch serialization control
— Synchronization for all instruction flow changes—interrupts, mispredicted branches,
and context-synchronizing instructions
• Issue queues
— Two-entry branch instruction issue queue (BIQ)
— Four-entry general instruction issue queue (GIQ)
• Branch unit—The branch unit (BU) is an execution unit and is distinct from the BPU. It
executes (resolves) all branch and CR logical instructions.
To Next Page
Loading...
