PowerPC e500 Core Family Reference Manual, Rev. 1
2-4 Freescale Semiconductor
Register Model
• Book E–defined special-purpose registers (SPRs) that are accessed explicitly using mtspr
and mfspr instructions. These registers are listed in Table 2-1 in Section 2.2.1,
“Special-Purpose Registers (SPRs).”
• Freescale EIS–defined SPRs and e500-defined SPRs that are accessed explicitly using the
mtspr and mfspr instructions. These registers are listed in Table 2-2 in Section 2.2.1,
“Special-Purpose Registers (SPRs).”
• Freescale EIS–defined performance monitor registers (PMRs). These registers are similar
to SPRs, but are accessed with EIS–defined move to and move from PMR instructions
(mtpmr and mfpmr).
Book E– and e500-defined SPRs are grouped by function as follows:
• Section 2.4, “Registers for Branch Operations.” This section includes descriptions of the
count register (CTR) and the link register (LR).
• Section 2.5, “Processor Control Registers”
• Section 2.6, “Timer Registers”
• Section 2.7, “Interrupt Registers”
• Section 2.8, “Software-Use SPRs (SPRG0–SPRG7 and USPRG0)”
• Section 2.9, “Branch Target Buffer (BTB) Registers”
• Section 2.10, “Hardware Implementation-Dependent Registers”
• Section 2.11, “L1 Cache Configuration Registers”
• Section 2.12, “MMU Registers”
• Section 2.13, “Debug Registers”
• Section 2.14, “SPE and SPFP APU Registers”
Book E defines 32- and 64-bit registers. All 32-bit registers are supported as defined in Book E.
However, except for the 64-bit FPRs, which are not implemented on the e500, only bits 32–63 of
Book E’s 64-bit registers (such as LR, CTR, the GPRs, SRR0, and CSRR0) are required to be
implemented in hardware in a 32-bit Book E implementation. The e500 implements 64-bit GPRs,
the upper 32 bits of which are used only with the e500-specific signal processing engine (SPE)
APU, embedded vector single-precision floating-point APU, and the e500v2 embedded scalar
double-precision floating-point APU instructions.
Likewise, all Book E integer instructions defined to return a 64-bit result return only bits 32–63 of
the result on a 32-bit Book E implementation. SPE APU vector instructions return 64-bit values,
as do DPFP APU instructions on the e500v2; SPFP APU instructions return single-precision
32-bit values.
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