Intel
ยฎ
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 271
Layout ChecklistโIntel
ยฎ
EP80579 Integrated Processor Product Line
DDR_A[14:0],
DDR_BA[2:0],
DDR_RAS#,
DDR_CAS#,
DDR_WE#
Zo = 40
ฮฉ +/- 10% single ended
Trace Width:
Brakeout Trace Width 4 mils
Stripline: 6.5 mils(L3/L8)
Airgap Spacing:
Brakeout spacing Min=4 mils
Between group signals
Min=15mils
To any other signals Min=20mils
EP80579 to First DIMM
2.0 in to 4.0 in Max
First to Second DIMM
Max=0.8 in
Total Trace Length (TTL)
2.0 in - 6.0 in
Termination Trace Length
Max = 0.5 in. Skew
between Termination
Trace Length should not
exceed 200 mils.
Skew: Match all group
signals within 20 mils.
The shortest signal of the
group must not exceed
the longest signal of the
group by 20 mils. This
requirement is for the
complete length from
EP80579 to the farthest
DIMM connector.
See Section 9.7, โDDR2 Interface
System Interconnectโ.
Topology Daisy Chain
Reference Plane:
Ground and Power reference
plane
Route groups of signals on the
same layer from EP80579 to the
farthest DIMM.
No vias, except were required to
breakout.
Place Ccomp caps as close as
possible to the DIMM
DDR_CS[1:0]#,
DDR_CKE[1:0],
DDR_ODT[1:0]
Zo = 40
ฮฉ +/- 10% single ended
Trace Width:
Brakeout Trace Width 4 mils
Stripline: 6.5 mils(L3/L8)
Airgap Spacing:
Brakeout spacing Min=4mils
Between group signals
Min=15mils
To any other signals Min=20mils
EP80579 to First DIMM
2.0 in to 4.0 in Max
First to Second DIMM
Max=0.8 in
Total Trace Length (TTL)
2.0 in - 6.0 in
Termination Trace Length
Max = 0.5 in. Skew
between Termination
Trace Length should not
exceed 200 mils.
Skew: Match all group
signals within 20 mils.
The shortest signal of the
group must not exceed
the longest signal of the
group by 20 mils. This
requirement is for the
complete length from
EP80579 to the farthest
DIMM connector.
See Section 9.7, โDDR2 Interface
System Interconnectโ.
Topology Daisy Chain
Reference Plane:
Ground and Power reference
plane
Route groups of signals on the
same layer from EP80579 to the
farthest DIMM.
No vias, except were required to
breakout.
Table 97. Layout Checklist (Sheet 3 of 13)
Signal Name
Trace Geometry and
Impedance
Length Requirements Comments
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