Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line—Layout Checklist
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
272 Order Number: 320068-005US
DDR_CK[5:0],
DDR_CK[5:0]#
Zo = 40
Ω +/- 10% single ended
Trace Width:
Brakeout Trace Width 4 mils
Stripline: 6.5 mils(L3/L8)
Airgap Spacing:
Brakeout spacing Min=4mils
DDR_CK to DDR_CK# 6mils
Pair to Pair Min=15mils
To any other signals Min=20mils
EP80579 to First DIMM
2.0 in to 4.0 in Max
Total Trace Length (TTL)
2.0 in - 6.0 in
DDR_CK to DDR_CK#
Match within 10 mils
Skew: Match all pair to
pair group within 20 mils.
The shortest pair of the
group must not exceed
the longest pair of the
group by 20 mils. This
requirement is for the
complete length from
EP80579 to the farthest
DIMM connector.
DDR_CK/DDR_CK# Clock
pairs should be match in
length to CMD/ADDR
within 20 mils
See Section 9.7, “DDR2 Interface
System Interconnect”.
Topology Point to Point
Groups are defined as follow:
First group CLK/CLK#[2:0]
Second group CLK/CLK#[5:3]
Reference Plane:
Ground and Power reference
plane.
Route Clock group on the same
layer from EP80579 to the
farthest DIMM.
No vias, except were required to
breakout.
DDR_CRES[0],
DDR_SLWCRES,
DDR_DRVCRES
DDR_RCOMPX
Trace Width:
Brakeout Trace Width 4 mils
Other routing 20 mils
Airgap Spacing:
Brakeout spacing Min=4mils
To any other signals Min=12mils
Total Trace Length (TTL)
Max=500mils
Keep traces as short as possible.
DDR_CRES[1],
DDR_CRES[2]
Trace Width:
Brakeout Trace Width 4 mils
Other routing 20 mils
Airgap Spacing:
Brakeout spacing Min=4mils
To any other signals Min=12mils
Total Trace Length (TTL)
Max=500mils
Keep traces as short as possible.
Place the RC circuit as close as
possible to EP80579.
PCI Express Interface
PEA0_Tp[7:0],
PEA0_Tn[7:0]
Zdiff = 90
Ω +/- 10%
Trace Width:
Brakeout Trace Width 4 mils
Microstrip: 4.75 mils
Stripline: 4.5 mils (L3/L8)
Airgap Spacing:
Brakeout spacing Min=4mils
Microstrip: 5.25 mils
Stripline: 5.5 mils
Spacing between Pairs, the
greater of the two
Microstrip: 20 mils or 3X
dielectric thickness.
Stripline: 18 mils or 3X dielectric
thickness.
Inter-pair length
matching: +/-5 mils.
Within a link, the lane-to-
lane skew should meet
the PCIe transmit skew
(tx-skew) specification.
See Section 10.1.7, “Topology 1
– EP80579 to PCI Express
Connector”.
Interface System Interconnect.
Maximum number of vias per
signal is 4.
Table 97. Layout Checklist (Sheet 4 of 13)
Signal Name
Trace Geometry and
Impedance
Length Requirements Comments

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English