Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 277
Layout Checklist—Intel
®
EP80579 Integrated Processor Product Line
THRMTRIP# Zo = 50
Ω +/- 10%
SLP_S3# Zo = 50 Ω +/- 10%
SLP_S4# Zo = 50
Ω +/- 10%
SLP_S5# Zo = 50
Ω +/- 10%
PWROK Zo = 50 Ω +/- 10%
PWRBTN# Zo = 50
Ω +/- 10%
RI# Zo = 50
Ω +/- 10%
SYS_RESET# Zo = 50
Ω +/- 10%
RSMRST# Zo = 50
Ω +/- 10%
SUS_STAT# Zo = 50
Ω +/- 10%
SUSCLK Zo = 50
Ω +/- 10%
VRMPWRGD Zo = 50 Ω +/- 10%
IERR# Zo = 50
Ω +/- 10%
IICH Miscellaneous Signals
CLK14
Zo = 50
Ω +/- 10%
Trace Width:
Microstrip: 5.5 mils
Stripline: 4.5 mils (L8)
Airgap Spacing:
Spacing to other signals
Min = 10mils
Spacing to non clock signals
Min = 10mils
Breakout:
Max = 500mils.
Length LT:
Max = 18 in.
Place damping resistor as close
as possible to the source.
WDT# Zo = 50
Ω +/- 10%
Acceleration and I/O Complex (AIOC)
Controller Area Network (CAN) Interface
CAN0TXD,
CAN1TXD
Zo = 50
Ω +/- 10%
CAN0TXEN,
CAN1TXEN
Zo = 50
Ω +/- 10%
CAN0RXD,
CAN1RXD
Zo = 50
Ω +/- 10%
Gigabit Ethernet (GbE) Interface
GBE0_TxCLK,
GBE1_TxCLK
GBE2_TxCLK
Zo = 55
Ω +/- 10%
Trace Width:
Brakeout Trace Width 4 mils
Microstrip: 4.5 mils
Stripline:
3.75 mils (L3/L8)
5 mils (L5/L6)
Airgap Spacing:
Brakeout spacing Min=4mils
Spacing to other clock signals
Stripline Min = 20mils
Microstrip Min = 25mils
Breakout:
EP80579 Max = 500mils.
PHY Max = 300mils.
Total Clock Routing:
Microstrip 1.5 to 7.8 in
Stripline 1 to 7.8 in.
Pull Up Trace Length
Max=0.4 in.
See Section 19.6.1.1, “GbE
Transmit Clock Topology”.
Place pull-up resistors close to
PHY device
Table 97. Layout Checklist (Sheet 9 of 13)
Signal Name
Trace Geometry and
Impedance
Length Requirements Comments

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English