Intel EP80579

Intel
®
EP80579 Integrated Processor Product Line—Schematics Checklist
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
287 Order Number: 320068-005US
DDR_CK[5:0],
DDR_CK[5:0]#
O
• Connect DDR_CK[2:0]/
DDR_CK[2:0]# from EP80579
to DIMM0.
• Connect DDR_CK[5:3]/
DDR_CK[5:3]# from EP80579
to DIMM1
•See Figure 79 and Figure 80
• Route clocks as differential signals
DDR_CRES[0],
DDR_SLWCRES,
DDR_DRVCRES
DDR_RCOMPX
I/O
• Connect DDR_SLWCRES to
DDR_CRES[0] with 825Ω ±1%
resistor.
• Connect DDR_DRVCRES to
DDR_CRES[0] with 249Ω ±1%
resistor.
• Connect DDR_RCOMPX to
DDR_CRES[0] with 825Ω ±1%
resistor.
•See Figure 83
DDR_CRES[1],
DDR_CRES[2]
I/O
• Connect DDR_CRES[1] to
ground with 100 Ω ±1%.
• Connect DDR_CRES[2] to
EP80579 1.8V
(VCC18) with
100 Ω ±1%.
• Decouple DDR_CRES[2] with
0.1 µF ±10%, 16V, capacitor to
GND.
•See Figure 84
PCI Express Interface
PEA0_Tp[7:0],
PEA0_Tn[7:0]
O
• Connect from EP80579 transmit
outputs to PCI Express Device
receive input pins through 0.1
µF ±10% AC blocking
capacitors.
• Signals should be routed as
differential pairs
•See Figure 94
•See Section 10.1.7 for Transmit
guidelines for EP80579 interface to
the PCI-E Connector
Note:
If a PCI-E port is not used or not
connected to an interfacing device,
terminate the transmit signals as
follows:
• PEA0_Tp[x]/PEA0_Tn[x] signals
may be left as no connect (NC)
(where ‘x’ is the PCIE port number
left unconnected)
PEA0_Rp[7:0],
PEA0_Rn[7:0]
I
• Connect from PCI Express
Device transmit outputs to
EP80579 receive inputs.
• Require external 0.1 µF ±10%
AC blocking capacitors on
Receive signals if the
Transmitting Device do not
have the suppression
capacitors built in at the
transmitter.
• Signals should be routed as
differential pairs
•See Figure 95
•See Section 10.1.7 for Receive
guidelines for EP80579 interface to
PCI-E Connector
Note:
If a PCI-E port is not used or not
connected to an interfacing device,
terminate the receive signals as follows:
• PEA0_Rp[x]/PEA0_Rn[x] signals
may be left as no connect (NC)
(where ‘x’ is the PCI-E port number
left unconnected)
Table 100. Schematic Checklist (Sheet 4 of 26)
Checklist Items
I/O Type
(Default)
Recommendations Comments