EasyManuals Logo

Intel EP80579 Guide

Intel EP80579
347 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #287 background imageLoading...
Page #287 background image
Intel
ยฎ
EP80579 Integrated Processor Product Lineโ€”Schematics Checklist
Intel
ยฎ
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
287 Order Number: 320068-005US
DDR_CK[5:0],
DDR_CK[5:0]#
O
โ€ข Connect DDR_CK[2:0]/
DDR_CK[2:0]# from EP80579
to DIMM0.
โ€ข Connect DDR_CK[5:3]/
DDR_CK[5:3]# from EP80579
to DIMM1
โ€ขSee Figure 79 and Figure 80
โ€ข Route clocks as differential signals
DDR_CRES[0],
DDR_SLWCRES,
DDR_DRVCRES
DDR_RCOMPX
I/O
โ€ข Connect DDR_SLWCRES to
DDR_CRES[0] with 825ฮฉ ยฑ1%
resistor.
โ€ข Connect DDR_DRVCRES to
DDR_CRES[0] with 249ฮฉ ยฑ1%
resistor.
โ€ข Connect DDR_RCOMPX to
DDR_CRES[0] with 825ฮฉ ยฑ1%
resistor.
โ€ขSee Figure 83
DDR_CRES[1],
DDR_CRES[2]
I/O
โ€ข Connect DDR_CRES[1] to
ground with 100 ฮฉ ยฑ1%.
โ€ข Connect DDR_CRES[2] to
EP80579 1.8V
(VCC18) with
100 ฮฉ ยฑ1%.
โ€ข Decouple DDR_CRES[2] with
0.1 ยตF ยฑ10%, 16V, capacitor to
GND.
โ€ขSee Figure 84
PCI Express Interface
PEA0_Tp[7:0],
PEA0_Tn[7:0]
O
โ€ข Connect from EP80579 transmit
outputs to PCI Express Device
receive input pins through 0.1
ยตF ยฑ10% AC blocking
capacitors.
โ€ข Signals should be routed as
differential pairs
โ€ขSee Figure 94
โ€ขSee Section 10.1.7 for Transmit
guidelines for EP80579 interface to
the PCI-E Connector
Note:
If a PCI-E port is not used or not
connected to an interfacing device,
terminate the transmit signals as
follows:
โ€ข PEA0_Tp[x]/PEA0_Tn[x] signals
may be left as no connect (NC)
(where โ€˜xโ€™ is the PCIE port number
left unconnected)
PEA0_Rp[7:0],
PEA0_Rn[7:0]
I
โ€ข Connect from PCI Express
Device transmit outputs to
EP80579 receive inputs.
โ€ข Require external 0.1 ยตF ยฑ10%
AC blocking capacitors on
Receive signals if the
Transmitting Device do not
have the suppression
capacitors built in at the
transmitter.
โ€ข Signals should be routed as
differential pairs
โ€ขSee Figure 95
โ€ขSee Section 10.1.7 for Receive
guidelines for EP80579 interface to
PCI-E Connector
Note:
If a PCI-E port is not used or not
connected to an interfacing device,
terminate the receive signals as follows:
โ€ข PEA0_Rp[x]/PEA0_Rn[x] signals
may be left as no connect (NC)
(where โ€˜xโ€™ is the PCI-E port number
left unconnected)
Table 100. Schematic Checklist (Sheet 4 of 26)
Checklist Items
I/O Type
(Default)
Recommendations Comments

Table of Contents

Other manuals for Intel EP80579

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Intel EP80579 and is the answer not in the manual?

Intel EP80579 Specifications

General IconGeneral
BrandIntel
ModelEP80579
CategoryComputer Hardware
LanguageEnglish

Related product manuals