Intel EP80579 - Page 293

Intel
®
EP80579 Integrated Processor Product Line—Schematics Checklist
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
293 Order Number: 320068-005US
SPI_MISO I
• Connect to the serial data
output pin of the flash device
• Connect signal
through a 15Ω
±1% series resistor
• Place resistor close to flash
device
Note:
• Must be pulled high to 3.3V through
a 10 KΩ resistor when the port is
not used.
SPI_CS# O
• Connect to the chip select
(CS#) pin of the flash device
• Connect signal
through a 15Ω
±1% series resistor
• Place series resistor close to
EP80579
• Pull-up to 3.3V through a 10
K
Ω resistor for signal stability
during power-up
Note:
• Can be left as NC when the port is
not connected to an interfacing
device.
SPI_CLK O
• Connect to the clock input pin
of the flash device
• Connect signal
through a 15Ω
±1% series resistor
• Place series resistor close to
EP80579.
Note:
• Can be left as NC when the port is
not connected to an interfacing
device.
System Management Bus (SMBus) Interface
SMBDATA/SMBCLK OD I/O
• Primary SMBus from EP80579
• Primary SMBus requires
external 8.2
kΩ pull-up resistors
to EP80579 3.3V Standby
voltage (VCCPSUS) on both
data and clock
• Connect Primary SMBus to
SuperIO and EP80579 IMCH
SMLINK
• Use Primary SMBus and
Repeaters to generate three
secondary SMBuses - (for
voltage translation, fanout, and
isolation)-
•
• SMBus_A - IMCH_SMBus
• SMBus_B - DIMM SMBus
• SMBus_C - MEZZ_SMBus
SMBus_A (IMCH_SMBus):
• Connects to EP80579 IMCH SMBus
(SMBSDA/SMBSCL)
• Connects to CK410 and clock buffer
DB800
• Connects to ITP-XDP Connector.
• Requires external 8.2
kΩ pull-up
resistors to platform VCC3 on both
data and clock.
SMBus_B (DIMM SMBus):
• Connects to DDR_DIMM0 and
DDR_DIMM1
• Requires external 8.2
kΩ pull-up
resistors to platform VCC3 on both
data and clock.
SMBus_C (MEZZ_SMBus):
• Connects to Mezzanine (0/1/2)
Connectors
• Requires external 8.2
kΩ pull-up
resistors to platform VCC3 on both
data and clock.
SMBSDA/SMBSCL OD I/O
• Connect to SMBus_A
(IMCH_SMBus)
Note:
• See the row above for SMBus_A
guidelines.
SMLINK[1:O] OD I/O
Connect to Primary SMBus:
• Connect SMLINK[0] to SMBCLK
• Connect SMLINK[1] to
SMBDATA
• SMBus System Management Link:
SMBus link to optional external
system management ASIC or LAN
controller
• Connect to Primary SMBus from
EP80579 (SMBDATA/SMBCLK)
• Primary SMBus requires external
8.2 kW pull-up resistors to EP80579
VCCPSUS power supply (3.3V
sustain power) on both data and
clock.
Table 100. Schematic Checklist (Sheet 10 of 26)
Checklist Items
I/O Type
(Default)
Recommendations Comments