Large Segment OffloadBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 111
LSO-Related Hardware Control Bits
The ISO Send Data Initiator Mode register is applicable only to controllers that have a secondary Tx ISO
(Isochronous) queue.
The ISO Read DMA Mode register is applicable only to controllers that have a secondary Tx ISO (Isochronous)
queue.
Note: In Broadcom controllers that have a physically separate isochronous (ISO) TX queue, there is
a parallel set of register fields, which mirror that of the normal TX path, for controlling LSO on the ISO
TX path.
Table 26: Send Data Initiator Mode Register (Offset: 0xC00)
Name Bits Access
Default
Value
Description
Hardware Pre-DMA Enable 3 RW 0 Enable hardware LSO pre-DMA processing
Table 27: ISO Send Data Initiator Mode Register (Offset: 0xD00)
Name Bits Access
Default
Value
Description
Hardware Pre-DMA Enable 3 RW 0 Enable hardware LSO pre-DMA processing
Table 28: Read DMA Mode Register (offset: 0x4800)
Name Bits Access
Default
Value
Description
Hardware IPv6 Post-DMA
Processing Enable
28 RW 1 Enable hardware processing of LSO IPv6 packets.
This bit has no effect on Post-DMA processing of
IPv4 packets. This bit when clear disables IPV6
Processing. This bit was not used for controllers
before BCM5718.
Hardware IPv4 Post-DMA
Processing Enable
27 RW 0 Enable hardware processing of LSO IPv4 packets.
This bit has no effect on Post-DMA processing of
IPv6 packets. This bit is the TCP Segmentation
Enable bit.
Table 29: ISO Read DMA Mode Register (Offset: 0x4A00)
Name Bits Access
Default
Value
Description
Hardware IPv6 Post-DMA
Processing Enable
28 RW 1 Enable hardware processing of LSO IPv6 packets.
This bit has no effect on Post-DMA processing of
IPv4 packets. This bit when clear disables IPV6
Processing. This bit was not used for controllers
before BCM5718.
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