PCI Configuration RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 297
DEVICE_CAPABILITY_2 – 0xd0
DEVICE_STATUS_CONTROL2 – 0xd4
Name Bits Access
Default
Value
Description
Unused1 31:12 RO 0 –
LTR_MECHANISM_SUPPORT
ED
11 RO 0 Latency Tolerance Reporting Mechanism
Supported, Programmable through register
space. This field will read 1, when bit 5 of
ext_cap_ena field in private register space is set.
Unused0 10:5 RO 0 –
CMPL_TIMEOUT_DISABL_
SUPPORTED
4 RO 0x1 Completion Timeout Disable Supported,
Programmable through register space
Path= i_cfg_func.i_cfg_private
CMPL_TIMEOUT_RANGES_
SUPPORTED
3:0 RO 0xf Completion Timeout Ranges Supported.
Programmable through register space
Path= i_cfg_func.i_cfg_private
Name Bits Access
Default
Value
Description
DEVICE_STATUS_2 31:16 RO 0 Placeholder for Gen2
Path= i_cfg_func.i_cfg_public.i_cfg_rd_mux
Unused 15:11 RO 0 –
LTR_MECHANISM_ENABLE 10 RW 0 Latency Tolerance Reporting Mechanism
Enable, This field is writeable, when bit 5 of
ext_cap_ena field in private register space is set.
This bit is RW only in function 0 and is RsvdP for
all other functions.
IDO_CPL_ENABLE 9 RW 0 IDO Completion Enable, This field is writeable,
when bit ido_supported bit of private
device_capability_2 register is set. When this bit
is set, function is permitted to set ID based
Ordering Attribute of Completions it returns.
IDO_REQ_ENABLE 8 RW 0 IDO Request Enable, This field is writeable,
when bit ido_supported bit of private
device_capability_2 register is set. When this bit
is set, function is permitted to set ID based
Ordering Attribute of Requests it initiates.
Unused0 7:5 RO 0 –
Value Name Description
15 ABCD Ranges A, B, C, and D
255 – end_of_table
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