Jumbo FramesBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 128
Figure 28: Receive Return Interface
Large Segment Offload (LSO/TSO)
LSO may create jumbo frames instead of standard sized frames. This is accomplished by programming the MSS
field of the send BD (see “Send Buffer Descriptor” on page 122).
The legacy NetXtreme design has limitations in LSO hardware. In the case of the BCM5718 family, these
limitations also exist. Below is the list of such limitations:
• MSS may not be less than 8 bytes
• LSO packet must be a TCP packet
• IP length field must not be incorrect
• TCP length field must not be incorrect
• Total offloaded TCP payload length must be greater than the MSS selected by SBD
• For all LSO segments, the SBD flag bit 8 and 9 (CPU pre-DMA and CPU post-DMA fields) must be set.
• LSO packet may not be IEEE 802.3 format with LLC and SNAP headers
• The total length of IP header (including IP option for IPv4, extension headers for IPv6) and TCP header
(including TCP option) may not be more than 200 bytes. Note: post_dma_proc can support only up to 2
MBUFs worth of packet header data. 1st Mbuf gives: 128, Mbuf-header (8B), Frame Header field (40B) =
80B; 2nd Mbuf gives: 128, Mbuf Header (8B) = 120B. Hence the total space for all headers, which includes
all L2/L3/L4 combined, and options cannot exceed 200 bytes.
Host Memory
RX Frame #1 (<= 1522B)
RX Std Host BD
RX Return Ring 0 Control
Block
RX Return Ring 0
Note: The RCB's host ring address field points to the first
element of the Ring in the host.
Status Word
Status Tag
RX Std Cons
031
Status Block
Rcv Return #1
TX Cons #1
Status Block (28 bytes)
The Status block resides in the NIC memory space
and is periodically DMA'd to the host whenever
the TX/RX coalescing timers expire, or whenever
the RX/TX max coalesced frames thresholds are
met. SW can examine the TX consumer indices in
the status block to determine which packets have
been sent by the HW.
The mailbox registers reside on-chip starting at offset
0x5800. Each mailbox register is 64 bits wide. Wrting the
lower 32 bits, triggers and event in the HW. SW updates the
TX Host Ring producer index to indicate that that there are
buffer descriptors ready for the HW to process.
Host Address
length
…...
031
Receive Buffer Descriptor
flags
Data Structures in the host
Data Structures kept on-chip
RX Ext Host BD
Rcv Return #3Rcv Return #2
Rcv Return #0
RX Jumbo Cons
Resvd
RX Std Cons Index references
a specific BD in the Std Ring
Host Ring Address
max_len
NIC Ring Address
0
31
flagsMax_frame_size
1st
Cons
Prod
1st
Cons
Prod
063
Mailbox Registers
RX Return Ring 0 Cons Index
RX Return Ring 3
063
Mailbox Registers
RX Return Ring 3 Cons Index
RX Return Ring 3 Control
Block
…...
Host Ring Address
max_len
NIC Ring Address
0
31
flags
R
X
F
r
a
m
e
#
2
(
<
=
9
6
2
2
B
)
RX Std Host BD
RX Frame #3 (<= 1522B)
There are 4 Receive Return Rings in the BCM5718
family when using RSS mode (16 if using IOV mode).
The Return Rings are host memory based – there are
cached copies inside the chip.
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