Broadcom NetXtreme/NetLink BCM5718 Series User Manual

Receive BD Completion Control RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 375
BD Fetch Limit Register (Offset 0x2D08)
This register is meaningful only in the IOV-Mode.
Receive BD Completion Control Registers
All registers reset are core reset unless specified.
Receive BD Completion Mode Register (offset: 0x3000)
Receive BD Completion Status Register (offset: 0x3004)
Table 106: BD Fetch Limit Register (Offset 0x2D08)
Name Bits Access
Default
Value
Description
Legacy 31:5 RU 0x0 Unused
BD Fetch Limit 4:0 RW 0x1F The number of BDs fetched by a single DMA
request shall be the lesser of the following:
• Space available in the respective BD cache.
• Standard or Jumbo Replenish Threshold.
• Number of BDs made available in the Host
memory based Ring.
• Programmed Value of this Field.
Name Bits Access
Default
Value
Description
Reserved 31:3 RO 0 –
Attention Enable 2 RW 0 When this bit is set to 1, an internal attention is
generated when an error occurs.
Enable 1 RW 1 This bit controls whether the Receive BD
Completion state machine is active or not. When
set to 0, it completes the current operation and
cleanly halts. Until it is completely halted, it
remains one when read.
Reset 0 RW 0 When this bit is set to 1, the Receive BD
Completion state machine is reset. This is a self-
clearing bit.
Name Bits Access
Default
Value
Description
Reserved 31:3 RO 0 –
Error 2 RO 0 Receive BD Completion Error Status.
Reserved 1:0 RO 0 –

Broadcom NetXtreme/NetLink BCM5718 Series Specifications

General

Brand	Broadcom
Model	NetXtreme/NetLink BCM5718 Series
Category	Controller
Language	English