RDMA RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 437
LSO/Non-LSO/BD Read DMA Corruption Enable Control Register
(offset: 0x4910)
Reserved 7 RW 0 –
Clock Request Fix Enable 6 RW 0 –
MBUF Threshold Clk Req 5:0 RW 0x7 –
Name Bits Access
Default
Value
Description
DTM stress failure 8bytes
duplication fix disable in
Non-LSO engine
31 RW 0 0: Enable fix
1: Disable fix
Reserved 30:28 RW 0 –
Disable fix in A1 for B2B Pcie
completion good pkt followed
by bad pkt (that is, packet with
LCRC error)
27 RW 0 0: Enable fix
1: Disable fix
Disable fix in A1 for B2B Pcie
completion good pkt followed
by good pkt
26 RW 0 0: Enable fix
1: Disable fix
Disable fix in A1 for DMA Read
engine miscalculation of
TXMBUF Available Space
25 RW 0 0: Enable fix
1: Disable fix
Disable fix in A1 for DMA Read
Underrun when running Core
Clk same speed as TL Clock
when CLKREQ is enabled
24 RW 0 0: Enable fix
1: Disable fix
Disable fix in A1 for RDMA
FIFO Overrun
23 RW 0 0: Enable fix
1: Disable fix
DTM stress failure DMA too
large error fix disable for Non-
LSO engine
22 RW 0 0: Enable fix
1: Disable fix
DTM stress test 8bytes
missing failure fix disable for
Non-LSO engine
21 RW 0 0: Enable fix
1: Disable fix
DTM stress failure corruption
fix disable for Non-LSO engine
20 RW 0 0: Enable fix
1: Disable fix
PCI Request Burst Length for
Non-LSO RDMA engine
19:18 RW 0 The two bits define the burst length that the Non-
LSO RDMA read engine would request to the
PCI block.
• 00 = 128B
• 01 = 256B
• 10 = 512B
•11 = 4KB
Name Bits Access
Default
Value
Description
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