DMA Completion RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 468
DMA Completion Registers
All registers reset are core reset unless specified.
DMA Completion Mode Register (offset: 0x6400)
GRC Registers
All registers reset are core reset unless specified.
Mode Control Register (offset: 0x6800)
Name Bits Access
Default
Value
Description
Reserved 31:2 RW – Reserved
Enable 1 RW 0 This bit controls whether the DMA Completion
state machine is active or not. When set to ‘0’ it
completes the current operation and cleanly
halts. Until it is completely halted it remains ‘1’
when read.
Reset 0 RW 0 When this bit is set to ‘1’ the DMA Completion
state machine is reset. This is a self-clearing bit.
Name Bits Access
Default
Value
Description
Pcie TL/DL/PL mapping bit 31 RW 0 Bit[31][22][29] remap PCIE core TL/DL/PL
register to GRC space from 0x6400 to 0x67ff.
[31]:
• 0: Select lower 1 KB of each TL/DL/PL
• 1 Select higher 1 KB of each TL/DL/Pl
[22][29]:
• 00: select TL register
• 01: select DL register
• 10: select PL register
Multicast enable 30 RW 0 Multicast enable bit.
Pcie TL/DL/PL mapping bit 29 RW – –
Interrupt on Flow Attention 28 RW 0 Cause a host interrupt when an enabled flow
attention occurs.
Interrupt on DMA Attention 27 RW 0 Cause a host interrupt when an enabled DMA
attention occurs.
Interrupt on MAC Attention 26 RW 0 Cause a host interrupt when an enabled MAC
attention occurs.
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