Broadcom NetXtreme/NetLink BCM5718 Series

Central Power Management Unit (CPMU) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 396
DLL Lock Timer Register (offset: 0x3654)
This register is reset by POR Reset or CPMU Register Software Reset.
CHIP ID Register (offset: 0x3658)
This register is reset by POR Reset or CPMU Register Software Reset.
Name Bits Access
Default
Value
Description
(BCM5718) Alternate Clock
Lock Timer
31:16 RW 0x61FF This parameter is used to preset the Alternate
DLL Lock Timer. This timer is always enabled.
Unit is in number of CPMU clock cycles
Range: up to 2
16
CPMU clock cycles
Default: 25088 CPMU clocks (1ms if CPMU clock
frequency is 25 MHz)
(BCM5719) NCSI PLL Lock
Timer
31:16 RW 0xF This parameter is used to preset the NCSI PLL
Lock Timer. This timer is always enabled.
Unit is in number of CPMU clock cycles
Range: up to 2
16
CPMU clock cycles
Default: 15 CPMU clocks
Reserved 15:11 DC 0 –
GPHY DLL Lock Timer 10:0 RW 0x3FF GPHY DLL Lock timer value.
Unit is in number of CPMU clock cycles
Range: up to 81920 CPMU clock cycles
Default: 1024 CPMU clocks (40.9 micro-seconds
if CPMU clock frequency is 25 MHz).
Name Bits Access
Default
Value
Description
Reserved 31:28 DC 0x0 –
Chip ID 27:12 RO 0x5717
0x5718
0x5719
–
Base Layer Revision
Information
11:8 RO 0000 Base layer revision history
0000: A0
0001: B0
0010: C0
Metal Layer Revision
Information
7:0 RO 0x0 Metal layer revision history