Central Power Management Unit (CPMU) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 407
EEE Mode Register (offset: 0x36B0)
EEE Debounce Timer 1 Control Register (offset: 0x36B4)
Name Bits Access
Default
Value
Description
Reserved 31:20 RO 0x0 –
Drive Allow LPI Enable 19 RW 0x0 Enable Control bit allocated for driver to allow
CPMU to go into EEE mode.
EEE Block Time 18:11 RW 0x0 Block out time from de-assertion of EEE MAC TX
request to when the EEE module considers new
request to enter LPI again.
Auto Wake Enable 10 RW 0x0 Enable automatic removal of Link from LPI state
when MAC wants to transmit.
RX LPI Enable 9 RW 0x0 Enable LPI indication in RX direction.
TX LPI Enable 8 RW 0x0 Enable LPI indication in TX direction.
User LPI Enable 7 RW 0x0 Main LPI enable bit set by user.
Send Index Detection Enable 6 RW 0x0 This bit allows CPMU to use the send consumer
and producer equal term to determine EEE
mode.
RX CPU Allow LPI Enable 5 RW 0x0 Enable Control bit allocated for RX CPU to allow
CPMU to go into EEE mode.
PCIE L1 Exit Detection Enable 4 RW 0x0 This bit allows CPMU to use the PCIE early L1
exit detection term to determine EEE mode.
EEE Link Idle Detection
Enable
3 RW 0x0 This bit allows CPMU to use the EEE link idle
detection term to determine EEE mode.
APE TX Detection Enable 2 RW 0x0 This bit allows CPMU to use the APE TX
detection term to determine EEE mode.
Drive Allow LPI 1 RW 0x0 Control bit allocated for driver to allow CPMU to
go into EEE mode.
RX CPU Allow LPI 0 RW 0x0 Control bit allocated for RX CPU to allow CPMU
to go into EEE mode.
Name Bits Access
Default
Value
Description
PCIE Early L1 Exit Debounce
Timer
31:16 RW 0x3F PCIE early L1 exit debounce timer in us.
Default is 63 µs.
EEE Link Idle Debounce Timer 15:0 RW 0x3F EEE link idle debounce timer in us.
Default is 63 µs.
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