TerminologyBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 579
Appendix B: Terminology
Table 156: Terminology
Term Definition
BD Buffer Descriptor.
Deferred Procedure Call
(DPC)
The ISR may schedule a O/S callback to process interrupts at a later time.
Expansion ROM PCI devices may optionally expose device specific programs to BIOS. For
example, network devices may place PXE boot code in their expansion ROM
region.
Host Coalescing A hardware block which the Ethernet controller status block. The hardware will
drive a line interrupt or MSI.
Interrupt Distribution Queue The Ethernet controller supports four interrupt distribution queues per class of
service. The rules engine may place traffic into RX return rings based on rules
checking. Within each class of service, the traffic may further be organized in
Interrupt Distribution Queues. For example, frames with errors may be given
lower data path priority over frames without errors, all within the same class of
service (RX Return Ring).
Interrupt Service Routine
(ISR)
A procedure where device interrupts are processed.
Pre-boot execution (PXE) An industry-standard client/server interface that allows networked computers
that are not yet loaded with an operating system to be configured and booted
remotely.
Receive BD Initiator The hardware block that DMA's BDs when receive ring indices are written.
Receive Data and Receive
BD Initiator
The hardware block the updates packet buffers, in host memory, after an
Ethernet frame is received. The hardware block will also update the BD with
information like checksum and VLAN Tags.
Receive Data Completion The hardware block that updates the host coalescing engine after the packet
buffers and BD are DMAed to host memory.
Receive Queue Placement The hardware block that routes a categorized frame to one of sixteen RX Return
rings.
Send BD Initiator The hardware block that is activated when a Send producer index is updated by
host software. The hardware block will DMA a BD from host memory.
Send Data Initiator The hardware block updates the DMAs in the packet buffers from host memory.
The packet buffers are DMAed after the BD has been moved to device local
memory.
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