Broadcom NetXtreme/NetLink BCM5718 Series User Manual

Host CoalescingBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 60
Host Coalescing
Host Coalescing Engine
The Host Coalescing Engine is responsible for pacing the rate at which the NIC updates the send and receive
ring indices located in host memory space. The completion of a NIC update is reflected through an interrupt on
the Ethernet controller INTA
pin or a Message Signaled Interrupt (MSI). Although update criteria are calculated
separately, all updates occur at once. This is because all of the ring indices are in one status block, and any host
update updates all ring indices simultaneously. The Host Coalescing Engine triggers based on a tick and/or a
frame counter.
Figure 7: Host Coalescing Engine
...
DMA
Write
Engine
Status Block
PCIe
Interface
Buffer
Manager
Host
Coalescing
Engine
MSI Mailbox
I/O
Driver
Host
Interrupt
Controller
IRQ
Write
FIFO
Tick
Counter
BD
Counter
Status
Memory
Host software may configure
line IRQ or MSI
MSI
FIFO

Broadcom NetXtreme/NetLink BCM5718 Series Specifications

General

Brand	Broadcom
Model	NetXtreme/NetLink BCM5718 Series
Category	Controller
Language	English