Wake on LAN Mode/Low-PowerBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 219
If the host software will be controlling the WOL configuration, it should write the DRV_WOL_SIGNATURE
(0x474c0000) to the shared memory address DRV_WOL_MAILBOX (0xd30) so that the boot code will not take
over the WOL initialization. If the DRV_WOL_SIGNATURE is not present, and WOL has been enabled, the boot
code will assume that the host software is a legacy driver and skip the WOL initialization. If WOL is disabled,
the boot code will take over the WOL initialization based on the NVRAM configuration.
PHY Auto-Negotiation
The integrated PHY should be configured to auto-negotiate for a 10 Mbps connection (see Tab le 79). This step
is required if the NIC must be placed into a D3 cold state. Half- or full-duplex operation is acceptable. Software
must modify auto-advertise configurations in the PHY’s MDI registers. The link partner will read advertisement
settings to find a highest common capability. Since WOL requires 10 Mbps wire speed, the two PHYs will
effectively auto-negotiate for half- or full-duplex connection.
Power Management
The clocking inputs need to be modified for WOL mode (see Table 80). The RX CPU is not required during WOL
operation, so its clock can be disabled. The MAC has an internal phase-locked loop that clocks internal logic at
133 MHz. Software must select an alternate clocking source and then disable this PLL.
The settings shown in Table 81 on page 220 enable Magic Packet detection logic in the MAC. These setting also
enable the MAC to assert PME on the PCI bus. The RX MAC should maintain the multicast and broadcast
settings that were previously configured by the NOS. The Microsoft
®
power management specification states:
Table 78: Firmware Mailbox Initialization
Name Address Recommended Value
T3_FIRMWARE_MAILBOX 0x0B50 0x4B657654
DRV_WOL_MAILBOX 0xd30 0x474c0000
Table 79: Recommended Settings for PHY Auto-Negotiation
Register Bit Recommended Value
Auto_Negotation_Advertisement 10_BASE_TX_Half_Duplex Enable
Auto_Negotation_Advertisement 10_BASE_TX_Full_Duplex Enable
Auto_Negotation_Advertisement 100_BASE_TX_Half_Duplex Disable
Auto_Negotation_Advertisement 100_BASE_TX_Full_Duplex Disable
1000BASE-T_Control 1000_BASE_TX_Half_Duplex Disable
1000BASE-T_Control 1000_BASE_TX_Full_Duplex Disable
Table 80: WOL Mode Clock Inputs
Register Bit Recommended Value
PCI Clock_Control RX RISC_Clock_Disable Set the bit to 1
PCI Clock_Control Select_Alternate_Clock Set the bit to 1
PCI Clock_Control PLL133 Set the bit to 1
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