Configuration SpaceBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 185
Figure 42: PCI Base Address Register
The Ethernet controller 64K memory mapped I/O block is determined by the first programmable bit in the BAR.
When the MAC is configured in standard mode, the mask 0xFFFF0000 identifies the BAR bits, which are
programmable. Bit 16 is the first bit encountered in the scan upward, which is programmable; bits 0–3 are
ignored. Host software will read zero values from bits 4–16. Figure 43 shows the BAR register and the bits
returned to the OS/BIOS during resource allocation.
Figure 43: PCI Base Address Register Bits Read in Standard Mode
Base Address P Type M
Memory Space Indicator:
I/O = 1
Memory = 0
Location:
00 = Anywhere
01 = Below 1 MB
10 = Anywhere in 64-bit Addr Space
11 = Reserved
Prefetchable:
0 = Disabled
1 = Enabled
Binary Weighted Value:
the 1st programmable
bit (ascending) indicates
requested block size.
[0][2:1][3][31:4]
XXXX XXXX XXXX XXX1 0000 0000 0000 0 11 0
[0][2:1][3][31:4]
Binary Weighted Value:
0x00010000 = 64K
X's are don't cares
Ignored:
Bits 0-3
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