Miscellaneous Control RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 481
TPH Hint Register (Offset: 0x68FC)
This register can enable TLP Hint assertion and Processing Hint on each Host Bound DMA transaction classes
individually.
Non-LSO Ch0 RDMA
FIFO tma control
9:8 RW 0x00 TM control for Ch0 non-LSO RDMA engine memory.
BD RDMA FIFO tmb
control
7:6 RW 0x00 TM control for BD RDMA engine memory.
BD RDMA FIFO tma
control
5:4 RW 0x00 TM control for BD RDMA engine memory.
LSO RDMA FIFO tmb
control
3:2 RW 0x00 TM control for LSO RDMA engine.
LSO RDMA FIFO tma
control
1:0 RW 0x00 TM control for LSO RDMA engine.
Name Bits
Acces
s
Default
Value
Description
Reserved 31:28 RW 0 –
MSI/MSI-X Vector Write Resvd 27 RW0 0 –
PH Value 26:25 RW 10 –
TH Enable 24 RW 0 –
Status Block Write Resvd 23 RW 0 –
PH Value 22:21 RW 10 –
TH Enable 20 RW 0 –
Receive Return BD Write Resvd 19 RW 0 –
PH Value 18:17 RW 10 –
TH Enable 16 RW 0 –
Packet Data Write Resvd 15 RW 0 –
PH Value 14:13 RW 10 –
TH Enable 12 RW 0 –
Receive Producer BD Read Resvd 11 RW 0 –
PH Value 10:9 RW 10 –
TH Enable 8 RW 0 –
Send BD Read Resvd 7 RW 0 –
PH Value 6:5 RW 10 –
TH Enable 4 RW 0 –
Packet Data Read Resvd 3 RW 0 –
PH Value 2:1 RW 10 –
TH Enable 0 RW 0 –
Name Bits Access
Default
Value
Description
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