Wake on LAN Mode/Low-PowerBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 218
Ta b le 7 7 shows an example of how 10/100 Mbps frame data is split up in the pattern data structure. Eight
streams are compared simultaneously with three 64-bit rows comprising one WOL entry. Rows 0–2 compare
frame data0 against eight rules. Rows 3–5 compare frame data1 against the next eight rules. Rows 6–9
compare data2 against the final eight rules. The eight rules may be uniquely defined for all three WOL entries.
Firmware Mailbox
When the Ethernet controller initializes (the firmware boot code is loaded from NVRAM when the chip powers
on or when reset completes), the boot code checks the T3_FIRMWARE_MAILBOX in shared memory. When
the T3_MAGIC_NUM signature (0x4B657654) is present, the boot code does not issue a hard reset to the PHY.
This is especially important in WOL mode since the PHY should not be reset.
Before the host software issues a reset to the Ethernet controller, it must write the T3_MAGIC_NUM to the
shared memory address T3_FIRMWARE_MAILBOX (0xb50). This address is a software mailbox, which boot
code polls before it resets the PHY. The boot code will acknowledge the signature by writing the one’s
complement of the T3_MAGIC_NUM back into the T3_FIRMWARE_MAILBOX. If the T3_MAGIC_NUM is
present, the boot code will not reset the PHY. After resetting the Ethernet controller, host software should poll
for the one’s complement of the T3_MAGIC_NUM before it proceeds, otherwise, boot code initialization may
interfere with the host software initialization.
58 S1 Low Byte Enable Enable S1 lower byte for comparison RW
57 S2 High Byte Enable Enable S2 higher byte for comparison RW
56 S2 Low Byte Enable Enable S2 lower byte for comparison RW
55:51 Reserved – –
50 S0 Done End of S0 Stream RW
49 S1 Done End of S1 Stream RW
48 S2 Done End of S2 Stream RW
Table 77: Example of Splitting 10/100 Mbps Frame Data in Pattern Data Structure
Data[63:48] Data[47:32] Data[31:16] Data[15:0]
Control Bits Stream 0 data 0 Stream 1 data 0 Stream 2 data 0
Control Bits Stream 3 data 0 Stream 4 data 0 Stream 5 data 0
Control Bits Stream 6 data 0 Stream 7 data 0 Stream 8 data 0
Control Bits Stream 0 data 1 Stream 1 data 1 Stream 2 data 1
Control Bits Stream 3 data 1 Stream 4 data 1 Stream 5 data 1
Control Bits Stream 6 data 1 Stream 7 data 1 Stream 8 data 1
Control Bits Stream 0 data 2 Stream 1 data 2 Stream 2 data 2
Control Bits Stream 3 data 2 Stream 4 data 2 Stream 5 data 2
Control Bits Stream 6 data 2 Stream 7 data 2 Stream 8 data 2
Table 76: Frame Control Field for 10/100 Mbps Mode (Cont.)
Bits Field Description Access
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