Ethernet MAC (EMAC) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 311
EMAC Status Register (offset: 0x404)
Tagged MAC Control 7 RW 0 Allow the MAC to receive tagged MAC control
packets.
Reserved 6:5 RO 0 –
Loopback mode 4 RW 0 When set, an internal loopback path is enabled
from the transmit MAC to the receive MAC. This
bit is provided for diagnostic purposes only.
Port Mode 3:2 RW 01 11: Obsolete (Was TBI)
10: 1000BT(Copper) GMII or SerDes 1000 mode
01: 10/100BT(Copper) MII or SerDes 10/100
mode
00: None
Half-duplex 1 RW 0 When set, the MII/GMII interface is configured to
operate in half-duplex mode and the CSMA/CD
state machines in the MAC are set to half-duplex
mode.
Global Reset 0 RW 0 When this bit is set to 1, the MAC state machine
is reset.
This is a self-clearing bit.
Name Bits Access
Default
Value
Description
Reserved 31:30 RO 0 –
Reserved. 29 RO 0 –
Interesting packet PME
Attention
28 W2C 0 When this bit is set, the WOL signal is asserted
when an interesting packet is detected.
TX Statistic Overrun 27 W2C 0 Transmit Statistics block has overrun.
Generates an attention when enabled.
RX Statistic Overrun 26 W2C 0 Receive Statistics block has overrun.
Generates an attention when enabled.
ODI Error 25 RO 0 Output Data Interface block has an overrun or
underrun.
Will generate attention when enabled.
Clear this attention using the Transmit Status
register.
AP Error 24 RO 0 Auto-polling interface needs service.
Generates an attention when enabled. Clear this
attention using the Auto-polling Status register
MII Interrupt 23 RO 0 Management interface is signaling an interrupt
Generates an attention when enabled.
Name Bits Access
Default
Value
Description
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