TCP Segmentation Control RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 349
VLAN Tag Register for TCP Segmentation (offset: 0xCF0)
Pre-DMA Command Exchange Register for TCP Segmentation
(offset: 0xCF4)
Invoke Processor 2 RW – Clears the Pass bit of the entry queued to the
SDCQ, so that SDC will invoke CPU.
• If the packet is created by hardware, this bit
will be the same as bit 9 of the flag field in
Send BD.
• If the packet is created by firmware, it will be
up to CPU whether it needs to post-process
the data.
Don't Generate CRC 1 RW – Do not generate CRC.
Pass through Send Buffer Descriptor flag.
No Byte Swap 0 RW – Set to disable endian byte swap on data from
PCIE bus.
Name Bits Access
Default
Value
Description
Reserved 31:16 RO 0 –
VLAN Tag 15:0 RW 0 VLAN Tag to be inserted into the Frame Header
if bit 7 of DMA Flags register is set.
Name Bits Access
Default
Value
Description
READY 31 RW 0 The CPU sets this bit to tell SDI that DMA
address, length, flags, and VLAN tag are valid
and request is read to go.
The CPU polls this bit to be clear for the
completion of request.
0xCF4.31 is writable only if 0xCE8.15:0 is
nonzero.
PASS Status 30 RO 1 If this bit is set to 0, the CPU will be responsible
for processing the buffer descriptor
SKIP Status 29 RW 0 The CPU sets this bit to 1 to inform the SDI that
the TCP Segmentation is completed, and the
BD_Index can be incremented.
Unsupported_Mss Status 28 RO 0 –
Reserved 27:7 RO 0 –
BD Index 6:0 RO 0 The internal current buffer descriptor pointer that
the hardware/firmware is servicing.
Name Bits Access
Default
Value
Description
To Next Page
Loading...
Need help?
General
