Receive Data Completion Control RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 371
Receive Data Completion Control Registers
All registers reset are core reset unless specified.
Receive Data Completion Mode Register (offset: 0x2800)
Name Bits Access
Default
Value
Description
Reserved 31:3 RO 0 –
Attention Enable 2 RW 0 When this bit is set to 1, an internal attention is
generated when an error occurs.
Enable 1 RW 1 This bit controls whether the Receive Data
Completion state machine is active or not. When
set to 0, it completes the current operation and
cleanly halts. Until it is completely halted, it
remains one when read.
Reset 0 RW 0 When this bit is set to 1, the Receive Data
Completion state machine is reset. This is a self-
clearing bit.
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