Broadcom NetXtreme/NetLink BCM5718 Series - Registers; Table 89: Interrupt-Related Registers

Host CoalescingBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 235
Registers
The Ethernet controller supports a variety of registers that affect status block updates and interrupt generation
(see Table 89).
Table 89: Interrupt-Related Registers
Register Cross Reference
Miscellaneous Host Control register.
The two bits of this register that are related to interrupts
are:
• Mask PCI Interrupt Output (aka Mask Interrupt) bit
• Clear Interrupt INTA
bit
“Miscellaneous Host Control Register (offset: 0x68)” on
page 282.
Miscellaneous Local Control register.
The two bits of this register that are related to interrupts
are:
• Set Interrupt bit
• Clear Interrupt bit
“Miscellaneous Local Control Register (offset: 0x6808)”
on page 471.
Interrupt Mailbox 0 register “Interrupt Mailbox 0 Register (offset: 0x5800)” on
page 460
Receive Coalescing Ticks register .“Receive Coalescing Ticks Register (offset: 0x3C08)”
on page 414
Send Coalescing Ticks register .“Send Coalescing Ticks Register (offset: 0x3C0C)” on
page 415
Receive Max Coalesced BD Count register .“Receive Max Coalesced BD Count Register (offset:
0x3C10)” on page 416
Send Max Coalesced BD Count register “Send Max Coalesced BD Count Register (offset:
0x3C14)” on page 418.
Mode Control register.
• Interrupt on Flow Attention (Bit 28) causes a host
interrupt when an enabled flow attention occurs
• Interrupt on DMA Attention (Bit 27) causes a host
interrupt when an enabled DMA attention occurs
• Interrupt on MAC Attention (Bit 26) causes a host
interrupt when an enabled MAC attention occurs
• Interrupt on RX RISC Attention (Bit 25) causes a
host interrupt when an enabled RX-RISC attention
occurs
“Mode Control Register (offset: 0x6800)” on page 468