VRQ Mapper RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 456
VRQ Mapper Registers
Each VRQ Mapper Entry is represented by a pair of 32-bit registers, named 1st Half of Entry and 2nd Half of
Entry. There shall be 18 such register pairs in order to map to 18 VRQ entries – including the Default VRQ and
the Drop VRQ. This register pair is used to program an SOP equation expressed as:
Filter Result = (Perf A AND/OR Set A) || (Perf B AND/OR Set B) || (Perf C AND/OR Set C) || (Perf D AND/OR
Set D).
Table 112: First Half VRQ Mapper Entry Register
Name Bits Access
Default
Value
Description
Product Term D
Reserved 31:30 RO 0 –
Activate Perfect Match in
this Term
29 RW 0 Write a 1 in this field to activate the Perfect Match
Address Reg selected by field [28:24].
Perfect Match Address
Reg #
28:24 RW 0x0 Write 0 – 23 in this field to select the Perfect Match
Address Reg Term D.
Product Term C
Reserved 23:22 RO 0 –
Activate Perfect Match in
this Term
21 RW 0 Write a 1 in this field to activate the Perfect Match
Address Reg selected by field [20:16]
Perfect Match Address
Reg #
20:16 RW 0x0 Write 0 – 23 in this field to select the Perfect Match
Address Reg for Term C.
Product Term B
Reserved 15:14 RO 0 –
Activate Perfect Match in
this Term
13 RW 0 Write a 1 in this field to activate the Perfect Match
Address Reg selected by field [12:8].
Perfect Match Address
Reg #
12:8 RW 0x0 Write 0 – 23 in this field to select the Perfect Match
Address Reg for Term B.
Product Term A
Reserved 7:6 RO 0 –
Activate Perfect Match in
this Term
5 RW 0 Write a 1 in this field to activate the Perfect Match
Address Reg selected by field [4:0].
Perfect Match Address
Reg #
4:0 RW 0x0 Write 0 – 23 in this field to select the Perfect Match
Address Reg for Term A.
Table 113: Second Half VRQ Mapper Entry Register
Name Bits Access
Default
Value
Description
Product Term D
Activate Product Term D 31 RW 0 Write a 1 to activate this whole Product Term.
To Next Page
Loading...
