Central Power Management Unit (CPMU) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 380
Link Speed 1000 MB Power Mode Clock Policy Register (offset:
0x360C)
This register is reset by POR Reset or CPMU Register Software Reset. Please note that clocks generated by
digital frequency multiplier could be up to 3% slower than intended clock speed. This register shall be
programmed to a different value only for engineering debug.
Name Bits Access
Default
Value
Description
Reserved 31:21 DC 0x0 –
MAC Clock Switch 20:16 RW 0x0 Software Controlled MAC Core Clock Speed
Select.
00000: Core = 62.5 MHz (GPHY DLL/2)
00001: Core = 60.0 MHz (Alt Source/2)
00011: Core = 30.0 MHz (Alt Source/4)
00101: Core = 15.0 MHz (Alt Source/8)
00111: Core = 7.5 MHz (Alt Source/16)
01001: Core = 3.75 MHz (Alt Source/32)
10001: Core = 12.5 MHz (CK25/2)
10011: Core = 6.25 MHz (CK25/4)
10101: Core = 3.125 MHz (CK25/8)
10111: Core = 1.563 MHz (CK25/16)
11001: Core = 781 kHz (CK25/32)
11111: Core = 12.5 MHz/1.25 MHz (MII_CLK/2)
Reserved 15:0 DC 0x0000 –
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