PCI Configuration RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 302
Uncorrectable Error Mask Register (offset: 0x108)
This register is reset by Hard Reset.
Name Bits Access
Default
Value
Description
Reserved 31:21 RO 0 –
Unsupported Request Error
Mask
20 RWS 0 Setting this bit will mask Unsupported Request
Error.
ECRC Error Mask 19 RWS 0 Setting this bit will mask ECRC error.
Malformed TLP Mask 18 RWS 0 Setting this bit will mask Malformed TLP error.
Receiver Overflow Mask 17 RWS 0 Setting this bit will mask Receiver overflow error.
Unexpected Completion Mask 16 RWS 0 Setting this bit will mask unexpected completion
error.
Completer Abort Mask 15 RWS 0 Setting this bit will mask completer abort error
Completion Timeout Mask 14 RWS 0 Setting this bit will mask completion timeout error.
Flow Control Protocol Error
Mask
13 RWS 0 Setting this bit will mask flow control protocol
error.
Poisoned TLP Mask 12 RWS 0 Setting this bit will mask poisoned TLP error.
Reserved 11:5 RO 0 –
Data Link Protocol Error Mask 4 RWS 0 Setting this bit will mask data link protocol error.
Reserved 3:1 RO 0 –
Training Error Mask 0 RWS 0 Setting this bit will mask training error.
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