Broadcom NetXtreme/NetLink BCM5718 Series - RX RISC Status Register (Offset: 0 X5004)

RX-CPU RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 452
RX RISC Status Register (offset: 0x5004)
The RX RISC State register reports the current state of the RX RISC and, if halted, gives reasons for the halt.
There are four categories of information; informational (read-only), informational (write-to-clear), disable-able
halt conditions (write-to-clear), and non-disable-able halt conditions (write-to-clear).
Enable Write Post Buffers 4 RW 0 Enables absorption of multiple software
operations for SRAM and register writes. When
this bit is disabled, only one write at a time will be
absorbed by the write post buffers. Cleared on
reset.
Note: Setting this bit on the BCM5705,
BCM5721, and BCM5751 may cause
unpredictable behavior.
Enable Page 0 Instr Halt 3 RW 0 When set, instruction references to the first 256
bytes of SRAM force the RX RISC to halt and
cause bit 4 in the RX RISC state register to be
latched. Cleared on reset and Watchdog
interrupt.
Enable Page 0 Data Halt 2 RW 0 When set, data references to the first 256 bytes
of SRAM force the RX RISC to halt and cause bit
3 in the RX RISC state register to be latched.
Cleared on reset and Watchdog interrupt.
Single-Step RX RISC 1 RW 0 Advances the RX RISC's PC for one cycle. If
halting condition still exists, the RX RISC will
again halt; otherwise, it will resume normal
operation.
Reset RX RISC 0 WO 0 Self-clearing bit which resets only the RX RISC.
Name Bits Access
Default
Value
Description
Blocking Read 31 RO 0 A blocking data cache miss occurred, causing
the RX RISC to stall while data is fetched from
external (to the RX RISC) memory. This is
intended as a debugging tool. No state is saved
other than the fact that the miss occurred.
MA Request FIFO overflow 30 W2C 0 MA_req_FIFO overflowed. The RX RISC is
halted on this condition.
MA data/bytemask FIFO
overflow
29 W2C 0 MA_datamask_FIFO overflowed. The RX RISC
is halted on this condition.
MA outstanding read FIFO
overflow
28 W2C 0 MA_rd_FIFO overflowed. The RX RISC is halted
on this condition.
MA outstanding write FIFO
overflow
27 W2C 0 MA_wr_FIFO overflowed. The RX RISC is halted
on this condition.
Reserved 26:16 RO 0 –
Instruction fetch stall 15 RO 0 The processor is currently stalled due to an
instruction fetch.
Name Bits Access
Default
Value
Description