RDMA RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 445
Non-LSO Read DMA Status Register (offset: 0x4B04)
Read DMA PCI Target Abort
Attention Enable
2 RO 0 Enable Read DMA PCI Target Abort Attention.
Enable 1 RO 1 This bit controls whether the Read DMA state
machine is active or not. When set to 0, it
completes the current operation and cleanly
halts. Until it is completely halted, it remains one
when read.
Reset 0 RO 0 When this bit is set to 1, the Read DMA state
machine is reset. This is a self-clearing bit.
Name Bits Access
Default
Value
Description
rdmad_length_d_0 31:16 RO 0 –
Reserved 15:11 RO 0 –
Read DMA PCI-X Split
Transaction Timeout Expired
10 W2C 0 Read DMA PCI-X split transaction timeout
expired.
Read DMA Local Memory
Write Longer Than DMA
Length Error
9 W2C 0 Read DMA Local Memory Write Longer Than
DMA Length Error.
Read DMA PCI FIFO Overread
Error
8 W2C 0 Read DMA PCI FIFO Overread Error (PCI read
longer than DMA length.)
Read DMA PCI FIFO Underrun
Error
7 W2C 0 Read DMA PCI FIFO Underrun Error.
Read DMA PCI FIFO Overrun
Error
6 W2C 0 Read DMA PCI FIFO Overrun Error.
Read DMA PCI Host Address
Overflow Error
5 W2C 0 Read DMA PCI Host Address Overflow Error. A
host address overflow occurs when a single DMA
read begins at an address below a multiple of
4 GB and ends at an address above the same
multiple of 4 GB (i.e., the host memory address
transitions from 0xXXXXXXXX_FFFFFFFF to
0xYYYYYYYY_00000000 in a single read). This
is a fatal error.
Read DMA PCI Parity Error 4 W2C 0 Read DMA PCI Parity Error.
Read DMA PCI Master Abort 3 W2C 0 Read DMA PCI Master Abort Error.
Read DMA PCI Target Abort 2 W2C 0 Read DMA PCI Target Abort Error.
Reserved 1:0 RO 3 –
Name Bits Access
Default
Value
Description
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