Broadcom NetXtreme/NetLink BCM5718 Series

MSI-X PlumbingBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 256
Each of these new sets have the same behavior or attribute as defined in “Receive Coalescing Ticks Register
(Offset: 0x3c08)” on page 253 and “Receive Max Coalesced Bd Count Register (Offset: 0x3c10)” on page 254,
except one aspect: when MSI-X Multivector mode is enabled, each of these sets associate with its respective
Status-Block[n]. However, when either MSI-X is disabled or MSI-X Single-Vector mode is enabled, none of these
additional sets would exist. Note that, when MSI-X Single-Vector mode is enabled, even though 5 (or 17) vectors
are advertised, only Vector#0 remains active.
Ta b le 1 0 0 summarizes the existence of HC Parameter Sets, and their association to Status-Blocks. An “----”
indicates that this register does not exist in this particular mode.
Note: To further clarify, in Legacy INTx mode, MSI mode, or MSI-X Single Vector mode, all Transmit
and Receive queues are metered collectively by HC Parameter Set [0]. Parameter Sets [1–16] do not
exist. Only in Multivector MSI-X mode do HC Parameter Sets [1–16] come into existence.
Table 100: MSI-X Host Coalescing Parameters
Valid
HC
Parameter
Register
Set
Invokes
Status
Block#
IOV-Mode +
Multiple TXQ
(Netqueue/ VMQ+TSS)
IOV-Mode +
Single TXQ
(VMQ)
RSS-Mode +
Multiple TXQ
(TSS)
RSS-Mode +
Single TXQ
(Legacy)
HC
Parameter
Registers
Address
Indication
Items
HC
Parameter
Registers
Address
Indication
Items
HC
Parameter
Registers
Address
Indication
Items
HC
Parameter
Registers
Address
Indication
Item
RCTR[0]
SCTR[0]
RMCBCR[0]
SMCBCR[0]
RMCBCDIR[0]
SMCBCDIR[0]
00x3C08
------
0x3C10
------
0x3C18
------
VRQ 0
LinkStat
Errors
VRQ Map
0x3C08
0x3C0C
0x3C10
0x3C14
0x3C20
0x3C24
VRQ 0
TX
LinkStat
Errors
VRQ Map
-----
-----
-----
-----
-----
-----
LinkStat
Errors
-----
0x3C0C
-----
0x3C14
-----
0x3C24
TX
LinkStat
Errors
RCTR[1]
SCTR[1]
RMCBCR[1]
SMCBCR[1]
RMCBCDIR[1]
SMCBCDIR[1]
10x3D80
0x3D84
0x3D88
0x3D8C
0x3D90
0x3D94
VRQ 1
TXQ 1
0x3D80
-----
0x3D88
-----
0x3D90
-----
VRQ 1
0x3D80
0x3D84
0x3D88
0x3D8C
0x3D90
0x3D94
RSS 0
TXQ 1
0x3D80
-----
0x3D88
-----
0x3D90
-----
RSS 0
RCTR[2]
SCTR[2]
RMCBCR[2]
SMCBCR[2]
RMCBCDIR[2]
SMCBCDIR[2]
20x3D98
0x3D9C
0x3DA0
0x3DA4
0x3DA8
0x3DAC
VRQ 2
TXQ 2
0x3D98
----
0x3DA0
-----
0x3DA8
-----
VRQ 2
0x3D98
0x3D9C
0x3DA0
0x3DA4
0x3DA8
0x3DAC
RSS 1
TXQ 2
0x3D98
----
0x3DA0
-----
0x3DA8
-----
RSS 1
RCTR[3]
SCTR[3]
RMCBCR[3]
SMCBCR[3]
RMCBCDIR[3]
SMCBCDIR[3]
30x3DB0
0x3DB4
0x3DB8
0x3DBC
0x3DC0
0x3DC4
VRQ 3
TXQ 3
0x3DB0
-----
0x3DB8
-----
0x3DC0
-----
VRQ 3
0x3DB0
0x3DB4
0x3DB8
0x3DBC
0x3DC0
0x3DC4
RSS 2
TXQ 3
0x3DB0
-----
0x3DB8
-----
0x3DC0
-----
RSS 2