SerDes PHY Register DefinitionsBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 554
When the link partner is in SGMII mode (bit-0 = 1), then:
Bit[15] = Link
Bit[14] = Acknowledge
Bit[13] = Duplex
Bit[11:10] = Speed
The other bits are reserved and should be zero.
AUTONEGEXPANSION
Register Description: Auto-negotiation expansion register.
Register Offset: 0x6 at Block 0
EXTENDEDSTATUS
Register Description: Extended status register.
Register Offset: 0xF at Block 0
Table 132: AUTONEGEXPANSION
Bits Name RW Description Default
15:3 RESERVED RO Reserved 0x000
2 NP_ABILITY RO Next page ability
0 = Local device is not next page capable.
1 = Local device is next page capable.
0
1 PG_REC RO Page received
0 = New link code word has not been received.
1 = Received new link code word.
0
0 RESERVED RO Reserved write 0, ignore read. 0
Table 133: EXTENDEDSTATUS
Bits Name RW Description Default
15 1000BASEX_FDX RO 0 = 1000Base-X full duplex not capable.
1 = 1000Base-X full duplex capable.
1
14 1000BASEX_HDX RO 0 = 1000Base-X half duplex not capable.
1 = 1000Base-X half duplex capable.
1
13 1000BASET_FDX RO 0 = 1000Base-T full duplex not capable.
1 = 1000Base-T full duplex capable.
0
12 1000BASET_HDX RO 0 = 1000Base-T half duplex not capable.
1 = 1000Base-T half duplex capable.
0
11:0 RESERVED RO Reserved write 0, ignore read. 0x000
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