SerDes PHY Register DefinitionsBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 559
1000XSTATUS1
Register Description: 1000X Status1 Register.
Register Offset: 0x14 at Block 0
6 FREQ_LOCK_ELASTICITY_T
X
RW 0 = Normal operation.
1 = Minimum FIFO latency to properly handle a
clock which is frequency locked, but out of phase.
(overrides bits [2:1] of this register).
Note: pll_clk125 and clk_in must be using the same
crystal.
1
5 FREQ_LOCK_ELASTICITY_
RX
RW 0 = Normal operation
1 = Minimum FIFO latency to properly handle a
clock which is frequency locked, but out of phase.
(Not necessary if MAC uses crs to determine
collision; overrides bits [2:1] of this register).
Note: MAC and PHY must be using the same
crystal for this mode to be enabled.
0
4 EARLY_PREAMBLE_RX RW 0 = Normal operation
1 = Send extra bytes of preamble to avoid FIFO
latency. (Not necessary if MAC uses crs to
determine collision)
0
3 EARLY_PREAMBLE_TX RW 0 = Normal operation
1 = Send extra bytes of preamble to avoid FIFO
latency. (Used in half-duplex applications to reduce
collision domain latency. MAC must send 5 bytes of
preamble or less to avoid non-compliant behavior.)
0
2:1 FIFO_ELASTICITY_TX_RX RW 00 = Supports packets up to 5 KB
01 = Supports packets up to 10 KB
1X = Supports packets up to 13.5 KB
0
0 TX_FIFO_RST RW 0 = Normal operation
1 = Reset transmit FIFO. FIFO will remain in reset
until this bit is cleared with a software write.
0
Table 137: 1000XSTATUS1
Bits Name RW Description Default
15 TXFIFO_ERR_DETEC
TED
RO 1 = Transmit FIFO error detected since last read.
0 = No transmit FIFO error detected since last read.
0
14 RXFIFO_ERR_DETEC
TED
RO 1 = Receive FIFO error detected since last read.
0 = No receive FIFO error detected since last read.
0
13 FALSE_CARRIER_DE
TECTED
RO 1 = False carrier detected since last read.
0 = No false carrier detected since last read.
0
Table 136: 1000XCONTROL3 (Cont.)
Bits Name RW Description Default
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