Jumbo FramesBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 123
Figure 25: Send Buffer Descriptor
• The Host Address is the 64-bit address where the send buffer is located in host memory.
• The Length[15:0] is the length of the frame or TCP large segment to be transmitted.
• The VLAN TAG[15:0] field is the tag to be inserted in the frame if flags[6] is set to 1.
• The aggregate HDRLEN[7:0] field is the length of the Ethernet+IP+TCP headers to be replicated in each
segment arising out of a large TCP segment (LSO). (See Flags also.)
• The MSS[13:0] field is the size of the TCP segments into which a LSO segment is to be chopped up into.
Note that it has been increased to hold the value of a jumbo frame size. The Flags field of SBD is shown in
Ta b le 3 4 below.
Table 34: Send Buffer Descriptor Flags
Bit # Flag Name Flag Description
0 TCP/UDP Checksum Offload
Enable
This bit enables calculation of TCP or UDP checksums for IPv4 and IPv6
transmitted packets. The driver sets this bit only if the packet contained
within a buffer is TCP or UDP over IPv4 or IPv6.
1 IP Checksum Offload Enable This bit enables calculation of the IPv4 layer-3 checksum. This bit is set
only for IPv4 packets. The driver never sets it for IPv6 packets.
2 Packet End This bit is set for the last send buffer in a packet.
3 Jumbo Frame Driver must set this bit to 1 if the MTU length of the Send Frame is >
1500B. The MTU length is the Ethernet payload length and excludes
header length (and trailer length).
All BDs belonging to a send packet must configure this bit identically.
4 HDRLEN[2] The length of the Ethernet+IP+TCP headers to be replicated in each
segment arising out of a large TCP segment (LSO).
5 Capture Time Stamp
(BCM5719/5720 only)
If this bit is 1, this frame’s launch time shall be captured in the TX Time-
Stamp Register.
6 VLAN TAG When this bit is set, the controller inserts a VLAN tag in the Ethernet
header. The value for the inserted tag is taken from the VLAN Tag field in
the send BD.
7 Coalesce Now If this bit is set, a status block with an updated send consumer index is
DMA'd to the host as soon as this buffer's data has been DMA'd from the
host. An interrupt may or may not be generated depending on the present
state of interrupt avoidance mechanisms.
8 CPU Pre-DMA If this bit is set, the CPU is required to act upon the buffer before the send
data initiator state machine is kicked off. Alternately, if hardware LSO is
enabled and this bit is set in conjunction with CPU post-DMA, then this
buffer is treated as part of an LSO segment to be further segmented by
hardware.
0x4
0x8
0xC
Host Address
0x0
Length[15:0]
HdrLen[1:0] MSS[13:0]
Flags
VLAN Tag[15:0]
31 15 0
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