Configuration SpaceBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 172
The header region is required by the PCI 2.2 specification. These registers must be implemented. The
capabilities registers are optional; however, they must adhere to section 6.7 of the PCI SIIG 2.2 specification.
Each capability has a unique ID, which is well-defined. The capabilities are chained using the Next Caps field,
in the capability register. The last capability will have a Next Caps field, which is zeroed.
The Device-Specific registers are shown in Ta b le 47.
Indirect Mode
Host software may use Indirect mode to access the Ethernet controller resources, without using Memory
Mapped I/O. Indirect mode shadows MAC resources to PCI configuration space registers. These shadow
registers can be read/written by system software through PCI configuration space registers. The Ethernet
controller Indirect mode registers expose the following MAC resources:
•Registers
• Local Memory
• Mailboxes
Indirect mode access can be used in conjunction with Standard mode PCI access. Indirect mode has no
interdependency on other PCI access modes and is a mode in itself.
Table 47: Device Specific Registers
Register Cross Reference
Miscellaneous Host Control “Miscellaneous Host Control Register (offset: 0x68)” on page 282.
PCI State “PCI State Register (offset: 0x70)” on page 285.
Register Base Address “Register Base Register (offset: 0x78)” on page 286.
Memory Base Address “Memory Base Register (offset: 0x7C)” on page 286.
Register Data “Register Data Register (offset: 0x80)” on page 286.
Memory Window Data “Memory Data Register (offset: 0x84)” on page 287.
UNDI Receive BD Standard Producer
Ring Producer Index Mailbox
“UNDI Receive BD Standard Producer Ring Producer Index Mailbox
Register (offset: 0x98–0x9C)” on page 287.
UNDI Receive Return Ring Consumer
Index Mailbox
“UNDI Receive Return Ring Consumer Index Register (offset: 0x88–
0x8C)” on page 287.
UNDI Send BD Producer Index Mailbox “UNDI Send BD Producer Index Mailbox Register (offset: 0x90–
0x94)” on page 287.
Note: Host software must assert the Indirect_Mode_Access bit in the Miscellaneous Host Control
register (see “Miscellaneous Host Control Register (offset: 0x68)” on page 282) to enable indirect
mode.
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