PCIBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 168
Section 9: PCI
Configuration Space
Description
PCI, PCI-X, and PCIe devices must implement sixteen 32-bit PCI registers. These registers are required for a
device to have PCI compliance. The format and layout of these registers is defined in the PCI 2.2 specification.
Capability registers provide system BIOS and Operating Systems visibility into a set of optional features, which
devices may implement. Although the capability registers are not required, the structure and mechanism for
chaining auxiliary capabilities is defined in the PCI specification. Both software and BIOS must implement
algorithms to fetch and program capabilities fields accordingly. Refer to section 6.7 of the PCI SIIG 2.2
specification. Additional PCI configuration space may be used for device-specific registers. However, device-
specific registers are not exposed to system software, according to a specification/standard. System software
cannot probe device specific registers without a predetermined understanding of the device and its functionality.
In summary, three types of PCI configuration space registers may be exposed by any particular device:
• Required
• Optional capabilities
• Device specific
Network devices implement large quantities of registers, and these registers could consume huge amounts of
PCI configuration space. PCI configuration access is not very efficient, on a performance basis.
Example: Intel x86 architectures use two I/O mapped I/O addresses 0xCF8 and 0xCFC for host-based
access to PCI configuration space. Should a host device driver access these I/O addresses on every device
read/write, CPU overhead would grow greatly. Generally, host device drivers should not use PCI
configuration space for standard I/O and control programming. There is one special case—Universal
Network Device Interface (UNDI) drivers. UNDI drivers may not have access to host memory mapped
registers when operating in real-mode; thus, an indirect mode of access is necessary. The Ethernet
controller implements a PCI indirect mode for memory, registers, and mailboxes access. A specific example
of a device driver, which uses indirect mode, is the Preboot Execution (PXE) driver. PXE drivers may be
stored in either option ROMs or directly in the system BIOS.
Note: The BCM5718 is PCIe v1.1 compliant.
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