Broadcom NetXtreme/NetLink BCM5718 Series User Manual

Buffer Manager RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 428
Memory Arbiter Trap Address Low Register (offset: 0x4008)
Memory Arbiter Trap Address High Register (offset: 0x400C)
Buffer Manager Registers
All registers reset are core reset unless specified.
Buffer Manager Mode Register (offset: 0x4400)
Name Bits Access
Default
Value
Description
Reserved 31:21 RO 0 –
MA Trap Addr Low 20:0 RW – Memory Arbiter Trap Address Low.
Name Bits Access
Default
Value
Description
Reserved 31:21 RO 0 –
MA Trap Addr High 20:0 RW – Memory Arbiter Trap Address High.
Name Bits Access
Default
Value
Description
TXFIFO Underrun Prevention
Enable
31 RW 0x1 1: Enable the EMAC TXFIFO underrun
prevention during LSO offload operation. It will
change the arbitration algorithm of TXMBUF
read requests to round-robin among CPU, PCIE,
RDMA and TXMAC. When TXFIFO is almost
empty, RDMA will hold its request till TXFIFO is
not almost empty.
0: Disable the EMAC TXFIFO underrun
prevention during LSO offload operation. The
arbitration algorithm of TXMBUF read requests
will be priority-based among CPU, PCIE, RDMA
and TXMAC. RDMA will ignore TXFIFO almost
empty alert.
Reserved 30:6 RO 0 –
Reset RXMBUF Pointer 5 RWC 0 When this bit is set, it will cause the RXMBUF
allocation and deallocation pointer to reset back
to the RXMBUF base. It will also cause the
RXMAC to drop the preallocated MBUF and
request a new one.
MBUF Low Attn Enable 4 RW 0 MBUF Low Attn Enable MBUF low attention
enable.

Broadcom NetXtreme/NetLink BCM5718 Series Specifications

General

Brand	Broadcom
Model	NetXtreme/NetLink BCM5718 Series
Category	Controller
Language	English