Broadcom NetXtreme/NetLink BCM5718 Series - Clock Status Register (Offset: 0 X3630)

Central Power Management Unit (CPMU) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 389
Clock Status Register (offset: 0x3630)
This register is reset by POR Reset or CPMU Register Software Reset.
Clock Status Register (offset: 0x3630)
This register is reset by POR Reset or CPMU Register Software Reset.
Note: This is for BCM5718. See “Clock Status Register (offset: 0x3630)” for BCM5719.
Name Bits Access
Default
Value
Description
Reserved 31:30 DC 0x0 –
Flash CLOCK Disable Status 29 RO – Flash clock disable status
Reserved 28 DC – Reserved
Reserved 27:26 RO – –
APE HCLK Disable Status 25 RO – APE HCLK clock disable status
APE FCLK Disable Status 24 RO – APE FCLK clock disable status
PERST_N status 23 RO – PERST_N status
Reserved 22:21 DC 0x0 –
MAC Clock Switch Status 20:16 RO – MAC Core Clock Speed Select Status
Reserved 15:13 DC 0x0 –
APE Clock Switch Status 12:8 RO – APE Clock Speed Select Status
Reserved 7 DC 0x0 –
Flash Clock Switch Status 6:4 RO – Flash Clock Speed Select Status
Reserved 3:0 DC 0x0 –
Note: This is for BCM5719. See “Clock Status Register (offset: 0x3630)” for BCM5718.
Name Bits Access
Default
Value
Description
Reserved 31:30 DC 0x0 –
Flash CLOCK Disable Status 29 RO – Flash clock disable status
Reserved 28:27 DC – –
Reserved 26 RO – –
APE FCLK Disable Status 25 RO – APE FCLK clock disable status
APE HCLK Disable Status 24 RO – APE HCLK clock disable status
Reserved 23:21 DC 0x0 –
MAC Clock Switch Status 20:16 RO – MAC Core Clock Speed Select Status