Central Power Management Unit (CPMU) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 381
Link Aware Power Mode Clock Policy Register (offset: 0x3610)
This register is reset by POR Reset or CPMU Register Software Reset. Please note that clocks generated by
digital frequency multiplier could be up to 3% slower than intended clock speed, and the clock source of the
clock policies programmed in this register must be the same as the host access clock policy register.
Name Bits Access
Default
Value
Description
Reserved 31:21 DC 0x000 –
MAC Clock Switch 20:16 RW 10111 Software Controlled MAC Core Clock Speed
Select.
00001: Core = 60.0 MHz (Alt Source/2)
00011: Core = 30.0 MHz (Alt Source/4)
00101: Core = 15.0 MHz (Alt Source/8)
00111: Core = 7.5 MHz (Alt Source/16)
01001: Core = 3.75 MHz (Alt Source/32)
10001: Core = 12.5 MHz (CK25/2)
10011: Core = 6.25 MHz (CK25/4)
10101: Core = 3.125 MHz (CK25/8)
10111: Core = 1.563 MHz (CK25/16)
11001: Core = 781 kHz (CK25/32)
11111: Core = 12.5 MHz/1.25 MHz (MII_CLK/2)
Reserved 15:13 RO 0x00 –
APE Clock Switch
(Reserved in BCM5719)
12:8 RW 10001 Software Controlled APE Clock Speed Select
00001: 60.0 MHz (Alt Source/2)
00011: 30.0 MHz (Alt Source/4)
00101: 15.0 MHz (Alt Source/8)
00111: 7.5 MHz (Alt Source/16)
01001: 3.75 MHz (Alt Source/32)
10001: 25.0 MHz (CK25)
10011: 12.5 MHz (CK25/2)
10101: 6.25 MHz (CK25/4)
10111: 3.125 MHz (CK25/8)
11001: 1.563 MHz (CK25/16)
Reserved 7:0 DC 0x0000 –
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