Memory Arbiter Control RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 426
Memory Arbiter Control Registers
All registers reset are core reset unless specified.
Memory Arbiter Mode Register (offset: 0x4000)
Name Bits Access
Default
Value
Description
Reserved 31:30 RO 0 –
CPU pipeline Request Disable 29 RW 0 When set to 1, the write/read requests from the
internal CPU will be processed sequentially.
Low Latency Enable 28 RW 0 When set to 1, the read from the CPU to the
RXMBUF will take the original MA protocol,
where data_rd_valid always goes after cmd_ack.
If set to 0, the data_rd_valid overlaps at the same
clock cycle as the cmd_ack.
Fast Path Read Disable 27 RW 0 Fast Path Read Disable. When set to 1, the read
from the CPU to the RXMBUF will take the slow
path that goes through the original memory
arbitration logic.
Reserved 26:21 RO 0 –
DMAW2 Addr Trap 20 RW 0 DMA Write 2 Memory Arbiter request trap
enable.
Reserved 19:17 RO 0 –
SDI Addr Trap Enable 16 RW 0 Send Data Initiator Memory Arbiter request trap
enable.
Reserved 15:13 RO 0 –
RDI2 Addr Trap Enable 12 RW 0 Receive Data Initiator 2 Memory Arbiter request
trap enable.
RDI1 Addr Trap Enable 11 RW 0 Receive Data Initiator 1 Memory Arbiter request
trap enable.
RQ Addr Trap Enable 10 RW 0 Receive List Placement Memory Arbiter request
trap enable.
Reserved 9 RO 0 –
PCI Addr Trap Enable 8 RW 0 PCI Memory Arbiter request trap enable.
Reserved 7 RO 0 –
RX RISC Addr Trap Enable 6 RW 0 RX RISC Memory Arbiter request trap enable.
DMAR1 Addr Trap Enable 5 RW 0 DMA Read 1 Memory Arbiter request trap
enable.
DMAW1 Addr Trap Enable 4 RW 0 DMA Write 1 Memory Arbiter request trap
enable.
RX-MAC Addr Trap Enable 3 RW 0 Receive MAC Memory Arbiter request trap
enable.
TX-MAC Addr Trap Enable 2 RW 0 Transmit MAC Memory Arbiter request trap
enable.
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