Message Signaled Interrupt RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 466
Message Signaled Interrupt Registers
All registers reset are core reset unless specified.
MSI Mode Register (offset: 0x6000)
Name Bits Access
Default
Value
Description
Reserved 31:21 RO 0 –
Valid Bit 20 RW 0 Set only if the head of RDIQ entry is valid.
Skip Bit 19 RW 0 If this bit is set, the head of RDIQ entry will be
popped.
Pass Bit 18 RW 0 This bit is 0 if RDIQ head entry is intended for the
CPU. It prevents the entry to be serviced by
WDMA.
Head RXMBUF Pointer 17:9 RO 0 Specifies the first MBUF of the RXMBUF cluster
for the received packet.
Tail RXMBUF Pointer 8:0 RO 0 Specifies the last MBUF of the RXMBUF cluster
for the received packet.
Name Bits Access
Default
Value
Description
Priority 31:30 RW 0 Sets the priority of the MSI engine relative to the
DMA read engine and DMA Write engine. Equal
settings result in fair round robin arbitration.
•00: Lowest
•01: Low
•10: High
• 11: Highest
(BCM5718) Reserved 29:11 RO 0 –
(BCM5719) Reserved 29:24 RO 0 –
(BCM5719) MSI ST Lower 23:16 RW 0x01 This 8-bit value is used as the TPH Steering Tag
when both TPH Interrupt Vector mode and MSI
mode are enabled.
(BCM5719) Reserved 15;11 RO 0 –
MSI Message 10:8 RW 0 This register sets the MSI message data bottom
bits to the value programmed here. This register
exists only for testing purposes and should
always be programmed to zero.
(BCM5718) Reserved 7 RO 0 –
(BCM5719) MSIX Multimode
Vector Enable
7RW0 –
MSI Byte Swap 6 0 –
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